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target/ppc: optimize p9 exception handling routines

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Currently, p9 exception handling has multiple if-condition checks where
it does an indirect access to pending_interrupts and LPCR via env.
Pass the values during entry to avoid multiple indirect accesses.

Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Harsh Prateek Bora 2024-10-10 11:17:35 +05:30 • committed by Nicholas Piggin
parent 7e806070f8
commit 2a05a63c1d
1 changed files with 39 additions and 33 deletions
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72
target/ppc/excp_helper.c
View file

@ -1872,60 +1872,65 @@ static int p8_next_unmasked_interrupt(CPUPPCState *env)
PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | PPC_INTERRUPT_FIT | \ PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | PPC_INTERRUPT_FIT | \
PPC_INTERRUPT_PIT | PPC_INTERRUPT_THERM) PPC_INTERRUPT_PIT | PPC_INTERRUPT_THERM)
static int p9_interrupt_powersave(CPUPPCState *env) static int p9_interrupt_powersave(CPUPPCState *env,
uint32_t pending_interrupts,
target_ulong lpcr)
{ {
/* External Exception */ /* External Exception */
if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && if ((pending_interrupts & PPC_INTERRUPT_EXT) &&
(env->spr[SPR_LPCR] & LPCR_EEE)) { (lpcr & LPCR_EEE)) {
bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); bool heic = !!(lpcr & LPCR_HEIC);
if (!heic || !FIELD_EX64_HV(env->msr) || if (!heic || !FIELD_EX64_HV(env->msr) ||
FIELD_EX64(env->msr, MSR, PR)) { FIELD_EX64(env->msr, MSR, PR)) {
return PPC_INTERRUPT_EXT; return PPC_INTERRUPT_EXT;
} }
} }
/* Decrementer Exception */ /* Decrementer Exception */
if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && if ((pending_interrupts & PPC_INTERRUPT_DECR) &&
(env->spr[SPR_LPCR] & LPCR_DEE)) { (lpcr & LPCR_DEE)) {
return PPC_INTERRUPT_DECR; return PPC_INTERRUPT_DECR;
} }
/* Machine Check or Hypervisor Maintenance Exception */ /* Machine Check or Hypervisor Maintenance Exception */
if (env->spr[SPR_LPCR] & LPCR_OEE) { if (lpcr & LPCR_OEE) {
if (env->pending_interrupts & PPC_INTERRUPT_MCK) { if (pending_interrupts & PPC_INTERRUPT_MCK) {
return PPC_INTERRUPT_MCK; return PPC_INTERRUPT_MCK;
} }
if (env->pending_interrupts & PPC_INTERRUPT_HMI) { if (pending_interrupts & PPC_INTERRUPT_HMI) {
return PPC_INTERRUPT_HMI; return PPC_INTERRUPT_HMI;
} }
} }
/* Privileged Doorbell Exception */ /* Privileged Doorbell Exception */
if ((env->pending_interrupts & PPC_INTERRUPT_DOORBELL) && if ((pending_interrupts & PPC_INTERRUPT_DOORBELL) &&
(env->spr[SPR_LPCR] & LPCR_PDEE)) { (lpcr & LPCR_PDEE)) {
return PPC_INTERRUPT_DOORBELL; return PPC_INTERRUPT_DOORBELL;
} }
/* Hypervisor Doorbell Exception */ /* Hypervisor Doorbell Exception */
if ((env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) && if ((pending_interrupts & PPC_INTERRUPT_HDOORBELL) &&
(env->spr[SPR_LPCR] & LPCR_HDEE)) { (lpcr & LPCR_HDEE)) {
return PPC_INTERRUPT_HDOORBELL; return PPC_INTERRUPT_HDOORBELL;
} }
/* Hypervisor virtualization exception */ /* Hypervisor virtualization exception */
if ((env->pending_interrupts & PPC_INTERRUPT_HVIRT) && if ((pending_interrupts & PPC_INTERRUPT_HVIRT) &&
(env->spr[SPR_LPCR] & LPCR_HVEE)) { (lpcr & LPCR_HVEE)) {
return PPC_INTERRUPT_HVIRT; return PPC_INTERRUPT_HVIRT;
} }
if (env->pending_interrupts & PPC_INTERRUPT_RESET) { if (pending_interrupts & PPC_INTERRUPT_RESET) {
return PPC_INTERRUPT_RESET; return PPC_INTERRUPT_RESET;
} }
return 0; return 0;
} }
static int p9_next_unmasked_interrupt(CPUPPCState *env) static int p9_next_unmasked_interrupt(CPUPPCState *env,
uint32_t pending_interrupts,
target_ulong lpcr)
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
/* Ignore MSR[EE] when coming out of some power management states */ /* Ignore MSR[EE] when coming out of some power management states */
bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset;
assert((env->pending_interrupts & P9_UNUSED_INTERRUPTS) == 0); assert((pending_interrupts & P9_UNUSED_INTERRUPTS) == 0);
if (cs->halted) { if (cs->halted) {
if (env->spr[SPR_PSSCR] & PSSCR_EC) { if (env->spr[SPR_PSSCR] & PSSCR_EC) {
@ -1933,7 +1938,7 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env)
* When PSSCR[EC] is set, LPCR[PECE] controls which interrupts can * When PSSCR[EC] is set, LPCR[PECE] controls which interrupts can
* wakeup the processor * wakeup the processor
*/ */
return p9_interrupt_powersave(env); return p9_interrupt_powersave(env, pending_interrupts, lpcr);
} else { } else {
/* /*
* When it's clear, any system-caused exception exits power-saving * When it's clear, any system-caused exception exits power-saving
@ -1944,14 +1949,14 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env)
} }
/* Machine check exception */ /* Machine check exception */
if (env->pending_interrupts & PPC_INTERRUPT_MCK) { if (pending_interrupts & PPC_INTERRUPT_MCK) {
return PPC_INTERRUPT_MCK; return PPC_INTERRUPT_MCK;
} }
/* Hypervisor decrementer exception */ /* Hypervisor decrementer exception */
if (env->pending_interrupts & PPC_INTERRUPT_HDECR) { if (pending_interrupts & PPC_INTERRUPT_HDECR) {
/* LPCR will be clear when not supported so this will work */ /* LPCR will be clear when not supported so this will work */
bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE); bool hdice = !!(lpcr & LPCR_HDICE);
if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) { if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) {
/* HDEC clears on delivery */ /* HDEC clears on delivery */
return PPC_INTERRUPT_HDECR; return PPC_INTERRUPT_HDECR;
@ -1959,18 +1964,18 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env)
} }
/* Hypervisor virtualization interrupt */ /* Hypervisor virtualization interrupt */
if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) { if (pending_interrupts & PPC_INTERRUPT_HVIRT) {
/* LPCR will be clear when not supported so this will work */ /* LPCR will be clear when not supported so this will work */
bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE); bool hvice = !!(lpcr & LPCR_HVICE);
if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hvice) { if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hvice) {
return PPC_INTERRUPT_HVIRT; return PPC_INTERRUPT_HVIRT;
} }
} }
/* External interrupt can ignore MSR:EE under some circumstances */ /* External interrupt can ignore MSR:EE under some circumstances */
if (env->pending_interrupts & PPC_INTERRUPT_EXT) { if (pending_interrupts & PPC_INTERRUPT_EXT) {
bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); bool lpes0 = !!(lpcr & LPCR_LPES0);
bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); bool heic = !!(lpcr & LPCR_HEIC);
/* HEIC blocks delivery to the hypervisor */ /* HEIC blocks delivery to the hypervisor */
if ((msr_ee && !(heic && FIELD_EX64_HV(env->msr) && if ((msr_ee && !(heic && FIELD_EX64_HV(env->msr) &&
!FIELD_EX64(env->msr, MSR, PR))) || !FIELD_EX64(env->msr, MSR, PR))) ||
@ -1980,20 +1985,20 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env)
} }
if (msr_ee != 0) { if (msr_ee != 0) {
/* Decrementer exception */ /* Decrementer exception */
if (env->pending_interrupts & PPC_INTERRUPT_DECR) { if (pending_interrupts & PPC_INTERRUPT_DECR) {
return PPC_INTERRUPT_DECR; return PPC_INTERRUPT_DECR;
} }
if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { if (pending_interrupts & PPC_INTERRUPT_DOORBELL) {
return PPC_INTERRUPT_DOORBELL; return PPC_INTERRUPT_DOORBELL;
} }
if (env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) { if (pending_interrupts & PPC_INTERRUPT_HDOORBELL) {
return PPC_INTERRUPT_HDOORBELL; return PPC_INTERRUPT_HDOORBELL;
} }
if (env->pending_interrupts & PPC_INTERRUPT_PERFM) { if (pending_interrupts & PPC_INTERRUPT_PERFM) {
return PPC_INTERRUPT_PERFM; return PPC_INTERRUPT_PERFM;
} }
/* EBB exception */ /* EBB exception */
if (env->pending_interrupts & PPC_INTERRUPT_EBB) { if (pending_interrupts & PPC_INTERRUPT_EBB) {
/* /*
* EBB exception must be taken in problem state and * EBB exception must be taken in problem state and
* with BESCR_GE set. * with BESCR_GE set.
@ -2020,7 +2025,8 @@ static int ppc_next_unmasked_interrupt(CPUPPCState *env)
case POWERPC_EXCP_POWER9: case POWERPC_EXCP_POWER9:
case POWERPC_EXCP_POWER10: case POWERPC_EXCP_POWER10:
case POWERPC_EXCP_POWER11: case POWERPC_EXCP_POWER11:
return p9_next_unmasked_interrupt(env); return p9_next_unmasked_interrupt(env, env->pending_interrupts,
env->spr[SPR_LPCR]);
default: default:
break; break;
} }