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cpu: Replace ENV_GET_CPU with env_cpu
Now that we have both ArchCPU and CPUArchState, we can define this generically instead of via macro in each target's cpu.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
2161a612b4
commit
29a0af618d
59 changed files with 175 additions and 197 deletions
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@ -587,7 +587,7 @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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tlb_flush_all_cpus_synced(cs);
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}
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@ -595,7 +595,7 @@ static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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tlb_flush_all_cpus_synced(cs);
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}
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@ -603,7 +603,7 @@ static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
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}
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@ -611,7 +611,7 @@ static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
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}
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@ -686,7 +686,7 @@ static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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tlb_flush_by_mmuidx(cs,
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ARMMMUIdxBit_S12NSE1 |
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@ -697,7 +697,7 @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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tlb_flush_by_mmuidx_all_cpus_synced(cs,
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ARMMMUIdxBit_S12NSE1 |
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@ -714,7 +714,7 @@ static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
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* translation information.
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* This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
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*/
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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uint64_t pageaddr;
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if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
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@ -729,7 +729,7 @@ static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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uint64_t pageaddr;
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if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
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@ -745,7 +745,7 @@ static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2);
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}
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@ -753,7 +753,7 @@ static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2);
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}
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@ -761,7 +761,7 @@ static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
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tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2);
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@ -770,7 +770,7 @@ static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
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tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
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@ -1921,7 +1921,7 @@ static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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uint64_t hcr_el2 = arm_hcr_el2_eff(env);
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uint64_t ret = 0;
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@ -3773,7 +3773,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
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static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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bool sec = arm_is_secure_below_el3(env);
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if (sec) {
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@ -3790,7 +3790,7 @@ static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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if (tlb_force_broadcast(env)) {
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tlbi_aa64_vmalle1is_write(env, NULL, value);
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@ -3861,7 +3861,7 @@ static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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* stage 2 translations, whereas most other scopes only invalidate
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* stage 1 translations.
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*/
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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bool sec = arm_is_secure_below_el3(env);
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bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
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@ -3884,7 +3884,7 @@ static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2);
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}
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@ -3892,7 +3892,7 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3);
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}
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@ -3975,7 +3975,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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uint64_t pageaddr = sextract64(value << 12, 0, 56);
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tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
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@ -3985,7 +3985,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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uint64_t pageaddr = sextract64(value << 12, 0, 56);
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tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
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@ -4017,7 +4017,7 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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uint64_t pageaddr;
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if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
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