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cpu: Replace ENV_GET_CPU with env_cpu
Now that we have both ArchCPU and CPUArchState, we can define this generically instead of via macro in each target's cpu.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
2161a612b4
commit
29a0af618d
59 changed files with 175 additions and 197 deletions
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@ -62,21 +62,21 @@
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#define ATOMIC_TRACE_RMW do { \
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uint8_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false); \
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\
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trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, info); \
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trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, \
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trace_guest_mem_before_exec(env_cpu(env), addr, info); \
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trace_guest_mem_before_exec(env_cpu(env), addr, \
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info | TRACE_MEM_ST); \
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} while (0)
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#define ATOMIC_TRACE_LD do { \
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uint8_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false); \
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\
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trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, info); \
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trace_guest_mem_before_exec(env_cpu(env), addr, info); \
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} while (0)
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# define ATOMIC_TRACE_ST do { \
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uint8_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, true); \
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\
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trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, info); \
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trace_guest_mem_before_exec(env_cpu(env), addr, info); \
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} while (0)
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/* Define host-endian atomic operations. Note that END is used within
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@ -415,7 +415,7 @@ static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_idx,
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CPUTLBDesc *d = &env_tlb(env)->d[mmu_idx];
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int k;
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assert_cpu_is_self(ENV_GET_CPU(env));
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assert_cpu_is_self(env_cpu(env));
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for (k = 0; k < CPU_VTLB_SIZE; k++) {
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if (tlb_flush_entry_locked(&d->vtable[k], page)) {
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tlb_n_used_entries_dec(env, mmu_idx);
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@ -883,7 +883,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
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int mmu_idx, target_ulong addr, uintptr_t retaddr,
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MMUAccessType access_type, int size)
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{
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CPUState *cpu = ENV_GET_CPU(env);
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CPUState *cpu = env_cpu(env);
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hwaddr mr_offset;
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MemoryRegionSection *section;
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MemoryRegion *mr;
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@ -927,7 +927,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
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int mmu_idx, uint64_t val, target_ulong addr,
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uintptr_t retaddr, int size)
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{
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CPUState *cpu = ENV_GET_CPU(env);
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CPUState *cpu = env_cpu(env);
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hwaddr mr_offset;
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MemoryRegionSection *section;
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MemoryRegion *mr;
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@ -979,7 +979,7 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
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{
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size_t vidx;
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assert_cpu_is_self(ENV_GET_CPU(env));
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assert_cpu_is_self(env_cpu(env));
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for (vidx = 0; vidx < CPU_VTLB_SIZE; ++vidx) {
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CPUTLBEntry *vtlb = &env_tlb(env)->d[mmu_idx].vtable[vidx];
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target_ulong cmp;
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@ -1029,7 +1029,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr)
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if (unlikely(!tlb_hit(entry->addr_code, addr))) {
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if (!VICTIM_TLB_HIT(addr_code, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0);
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tlb_fill(env_cpu(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0);
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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}
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@ -1067,7 +1067,7 @@ void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
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if (!tlb_hit(tlb_addr_write(entry), addr)) {
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/* TLB entry is for a different page */
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if (!VICTIM_TLB_HIT(addr_write, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE,
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tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE,
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mmu_idx, retaddr);
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}
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}
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@ -1101,7 +1101,7 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
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uintptr_t index = tlb_index(env, mmu_idx, addr);
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if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page)) {
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CPUState *cs = ENV_GET_CPU(env);
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CPUState *cs = env_cpu(env);
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CPUClass *cc = CPU_GET_CLASS(cs);
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if (!cc->tlb_fill(cs, addr, 0, access_type, mmu_idx, true, 0)) {
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@ -1144,7 +1144,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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/* Enforce guest required alignment. */
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if (unlikely(a_bits > 0 && (addr & ((1 << a_bits) - 1)))) {
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/* ??? Maybe indicate atomic op to cpu_unaligned_access */
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cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
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cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE,
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mmu_idx, retaddr);
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}
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@ -1160,7 +1160,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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/* Check TLB entry and enforce page permissions. */
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if (!tlb_hit(tlb_addr, addr)) {
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if (!VICTIM_TLB_HIT(addr_write, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_STORE,
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tlb_fill(env_cpu(env), addr, 1 << s_bits, MMU_DATA_STORE,
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mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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tlbe = tlb_entry(env, mmu_idx, addr);
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@ -1177,7 +1177,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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/* Let the guest notice RMW on a write-only page. */
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if (unlikely(tlbe->addr_read != (tlb_addr & ~TLB_NOTDIRTY))) {
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tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_LOAD,
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tlb_fill(env_cpu(env), addr, 1 << s_bits, MMU_DATA_LOAD,
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mmu_idx, retaddr);
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/* Since we don't support reads and writes to different addresses,
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and we do have the proper page loaded for write, this shouldn't
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@ -1190,7 +1190,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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ndi->active = false;
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if (unlikely(tlb_addr & TLB_NOTDIRTY)) {
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ndi->active = true;
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memory_notdirty_write_prepare(ndi, ENV_GET_CPU(env), addr,
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memory_notdirty_write_prepare(ndi, env_cpu(env), addr,
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qemu_ram_addr_from_host_nofail(hostaddr),
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1 << s_bits);
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}
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@ -1198,7 +1198,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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return hostaddr;
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stop_the_world:
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cpu_loop_exit_atomic(ENV_GET_CPU(env), retaddr);
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cpu_loop_exit_atomic(env_cpu(env), retaddr);
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}
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#ifdef TARGET_WORDS_BIGENDIAN
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@ -1263,7 +1263,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
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/* Handle CPU specific unaligned behaviour */
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if (addr & ((1 << a_bits) - 1)) {
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cpu_unaligned_access(ENV_GET_CPU(env), addr, access_type,
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cpu_unaligned_access(env_cpu(env), addr, access_type,
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mmu_idx, retaddr);
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}
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@ -1271,7 +1271,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
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if (!tlb_hit(tlb_addr, addr)) {
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if (!victim_tlb_hit(env, mmu_idx, index, tlb_off,
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addr & TARGET_PAGE_MASK)) {
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tlb_fill(ENV_GET_CPU(env), addr, size,
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tlb_fill(env_cpu(env), addr, size,
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access_type, mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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@ -1292,7 +1292,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
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* repeat the MMU check here. This tlb_fill() call might
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* longjump out if this access should cause a guest exception.
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*/
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tlb_fill(ENV_GET_CPU(env), addr, size,
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tlb_fill(env_cpu(env), addr, size,
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access_type, mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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@ -1511,7 +1511,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
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/* Handle CPU specific unaligned behaviour */
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if (addr & ((1 << a_bits) - 1)) {
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cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
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cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE,
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mmu_idx, retaddr);
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}
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@ -1519,7 +1519,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
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if (!tlb_hit(tlb_addr, addr)) {
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if (!victim_tlb_hit(env, mmu_idx, index, tlb_off,
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addr & TARGET_PAGE_MASK)) {
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tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE,
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tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE,
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mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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@ -1540,7 +1540,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
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* repeat the MMU check here. This tlb_fill() call might
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* longjump out if this access should cause a guest exception.
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*/
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tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE,
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tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE,
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mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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@ -1580,7 +1580,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
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if (!tlb_hit_page(tlb_addr2, page2)
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&& !victim_tlb_hit(env, mmu_idx, index2, tlb_off,
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page2 & TARGET_PAGE_MASK)) {
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tlb_fill(ENV_GET_CPU(env), page2, size, MMU_DATA_STORE,
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tlb_fill(env_cpu(env), page2, size, MMU_DATA_STORE,
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mmu_idx, retaddr);
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}
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@ -146,7 +146,7 @@ uint64_t HELPER(ctpop_i64)(uint64_t arg)
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void *HELPER(lookup_tb_ptr)(CPUArchState *env)
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{
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CPUState *cpu = ENV_GET_CPU(env);
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CPUState *cpu = env_cpu(env);
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TranslationBlock *tb;
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target_ulong cs_base, pc;
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uint32_t flags;
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@ -165,5 +165,5 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env)
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void HELPER(exit_atomic)(CPUArchState *env)
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{
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cpu_loop_exit_atomic(ENV_GET_CPU(env), GETPC());
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cpu_loop_exit_atomic(env_cpu(env), GETPC());
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}
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@ -1732,7 +1732,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
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tcg_func_start(tcg_ctx);
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tcg_ctx->cpu = ENV_GET_CPU(env);
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tcg_ctx->cpu = env_cpu(env);
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gen_intermediate_code(cpu, tb, max_insns);
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tcg_ctx->cpu = NULL;
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@ -680,7 +680,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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{
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/* Enforce qemu required alignment. */
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if (unlikely(addr & (size - 1))) {
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cpu_loop_exit_atomic(ENV_GET_CPU(env), retaddr);
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cpu_loop_exit_atomic(env_cpu(env), retaddr);
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}
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helper_retaddr = retaddr;
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return g2h(addr);
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