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target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes

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Per the nanoMIPS32 Instruction Set Technical Reference Manual,
Revision 01.01, Chapter 3. "Instruction Definitions":

The Read/Write Previous GPR opcodes "require CP0 privilege".

Add the missing CP0 checks.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210421185007.2231855-1-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-04-21 20:39:15 +02:00
parent 84c2fdc397
commit 298d43c96b
1 changed files with 2 additions and 0 deletions
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2
target/mips/translate.c
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@ -18969,9 +18969,11 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
} }
break; break;
case NM_RDPGPR: case NM_RDPGPR:
check_cp0_enabled(ctx);
gen_load_srsgpr(rs, rt); gen_load_srsgpr(rs, rt);
break; break;
case NM_WRPGPR: case NM_WRPGPR:
check_cp0_enabled(ctx);
gen_store_srsgpr(rs, rt); gen_store_srsgpr(rs, rt);
break; break;
case NM_WAIT: case NM_WAIT: