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target-mips: fix calculation of overflow for SHLL.PH and SHLL.QB

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This change corrects and simplifies how discard is calculated for shift
left logical vector instructions. It is used to detect overflow and set bit
22 in the DSPControl register.

The existing tests (shll_ph.c, shll_qb.c) are extended with the corner cases
that expose incorrectness in the previous implementation.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Petar Jovanovic 2013-04-28 03:18:36 +02:00 • committed by Aurelien Jarno
parent 8ca27ce2e1
commit 29851ee7c8
3 changed files with 59 additions and 27 deletions
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33
tests/tcg/mips/mips32-dsp/shll_ph.c
View file

@ -11,7 +11,38 @@ int main()
resultdsp = 1;
__asm
("shll.ph %0, %2, 0x0B\n\t"
("wrdsp $0\n\t"
"shll.ph %0, %2, 0x0B\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dsp)
: "r"(rt)
);
dsp = (dsp >> 22) & 0x01;
assert(dsp == resultdsp);
assert(rd == result);
rt = 0x7fff8000;
result = 0xfffe0000;
resultdsp = 1;
__asm
("wrdsp $0\n\t"
"shll.ph %0, %2, 0x01\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dsp)
: "r"(rt)
);
dsp = (dsp >> 22) & 0x01;
assert(dsp == resultdsp);
assert(rd == result);
rt = 0x00000001;
result = 0x00008000;
resultdsp = 1;
__asm
("wrdsp $0\n\t"
"shll.ph %0, %2, 0x0F\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dsp)
: "r"(rt)

23
tests/tcg/mips/mips32-dsp/shll_qb.c
View file

@ -11,12 +11,14 @@ int main()
resultdsp = 0x00;
__asm
("shll.qb %0, %2, 0x00\n\t"
("wrdsp $0\n\t"
"shll.qb %0, %2, 0x00\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dsp)
: "r"(rt)
);
dsp = (dsp >> 22) & 0x01;
assert(dsp == resultdsp);
assert(rd == result);
rt = 0x87654321;
@ -24,12 +26,29 @@ int main()
resultdsp = 0x01;
__asm
("shll.qb %0, %2, 0x03\n\t"
("wrdsp $0\n\t"
"shll.qb %0, %2, 0x03\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dsp)
: "r"(rt)
);
dsp = (dsp >> 22) & 0x01;
assert(dsp == resultdsp);
assert(rd == result);
rt = 0x00000001;
result = 0x00000080;
resultdsp = 0x00;
__asm
("wrdsp $0\n\t"
"shll.qb %0, %2, 0x07\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dsp)
: "r"(rt)
);
dsp = (dsp >> 22) & 0x01;
assert(dsp == resultdsp);
assert(rd == result);
return 0;