motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-09-02 06:51:53 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

hw/acpi/piix4: use qdev gpio to wire up sci_irq

Browse source 
Introduce piix4_pm_init() instance init function and use it to
initialise the separate qdev gpio for the SCI IRQ.

The sci_irq can now be wired up directly using a qdev gpio instead
of having to set the IRQ externally in piix4_pm_initfn().

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220528091934.15520-9-mark.cave-ayland@ilande.co.uk>
[PMD: Partially squash 20220528091934.15520-8-mark.cave-ayland@ilande.co.uk]
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Mark Cave-Ayland 2022-05-28 10:02:11 +01:00 • committed by Philippe Mathieu-Daudé
parent d0af99ac12
commit 29786d42ba
4 changed files with 15 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

12
hw/acpi/piix4.c
View file

@ -497,9 +497,15 @@ static void piix4_pm_realize(PCIDevice *dev, Error **errp)
piix4_pm_add_properties(s); piix4_pm_add_properties(s);
} }
static void piix4_pm_init(Object *obj)
{
PIIX4PMState *s = PIIX4_PM(obj);
qdev_init_gpio_out(DEVICE(obj), &s->irq, 1);
}
PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base, PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq, qemu_irq smi_irq, bool smm_enabled)
bool smm_enabled)
{ {
PCIDevice *pci_dev; PCIDevice *pci_dev;
DeviceState *dev; DeviceState *dev;
@ -511,7 +517,6 @@ PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base,
qdev_prop_set_bit(dev, "smm-enabled", smm_enabled); qdev_prop_set_bit(dev, "smm-enabled", smm_enabled);
s = PIIX4_PM(dev); s = PIIX4_PM(dev);
s->irq = sci_irq;
s->smi_irq = smi_irq; s->smi_irq = smi_irq;
pci_realize_and_unref(pci_dev, bus, &error_fatal); pci_realize_and_unref(pci_dev, bus, &error_fatal);
@ -663,6 +668,7 @@ static void piix4_pm_class_init(ObjectClass *klass, void *data)
static const TypeInfo piix4_pm_info = { static const TypeInfo piix4_pm_info = {
.name = TYPE_PIIX4_PM, .name = TYPE_PIIX4_PM,
.parent = TYPE_PCI_DEVICE, .parent = TYPE_PCI_DEVICE,
.instance_init = piix4_pm_init,
.instance_size = sizeof(PIIX4PMState), .instance_size = sizeof(PIIX4PMState),
.class_init = piix4_pm_class_init, .class_init = piix4_pm_class_init,
.interfaces = (InterfaceInfo[]) { .interfaces = (InterfaceInfo[]) {

4
hw/i386/pc_piix.c
View file

@ -283,9 +283,9 @@ static void pc_init1(MachineState *machine,
PIIX4PMState *piix4_pm; PIIX4PMState *piix4_pm;
smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0);
piix4_pm = piix4_pm_initfn(pci_bus, piix3_devfn + 3, 0xb100, piix4_pm = piix4_pm_initfn(pci_bus, piix3_devfn + 3, 0xb100, smi_irq,
x86ms->gsi[9], smi_irq,
x86_machine_is_smm_enabled(x86ms)); x86_machine_is_smm_enabled(x86ms));
qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]);
pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c")); pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c"));
/* TODO: Populate SPD eeprom data. */ /* TODO: Populate SPD eeprom data. */
smbus_eeprom_init(pcms->smbus, 8, NULL, 0); smbus_eeprom_init(pcms->smbus, 8, NULL, 0);

6
hw/isa/piix4.c
View file

@ -311,9 +311,9 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci"); pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci");
if (smbus) { if (smbus) {
pms = piix4_pm_initfn(pci_bus, devfn + 3, 0x1100, pms = piix4_pm_initfn(pci_bus, devfn + 3, 0x1100, NULL, 0);
qdev_get_gpio_in_named(dev, "isa", 9), qdev_connect_gpio_out(DEVICE(pms), 0,
NULL, 0); qdev_get_gpio_in_named(dev, "isa", 9));
*smbus = I2C_BUS(qdev_get_child_bus(DEVICE(pms), "i2c")); *smbus = I2C_BUS(qdev_get_child_bus(DEVICE(pms), "i2c"));
} }

3
include/hw/southbridge/piix.h
View file

@ -17,8 +17,7 @@
#include "hw/acpi/piix4.h" #include "hw/acpi/piix4.h"
PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base, PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq, qemu_irq smi_irq, bool smm_enabled);
bool smm_enabled);
/* PIRQRC[A:D]: PIRQx Route Control Registers */ /* PIRQRC[A:D]: PIRQx Route Control Registers */
#define PIIX_PIRQCA 0x60 #define PIIX_PIRQCA 0x60