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hw/intc/arm_gicv3: Add NMI handling CPU interface registers
Add the NMIAR CPU interface registers which deal with acknowledging NMI. When introduce NMI interrupt, there are some updates to the semantics for the register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it should return 1022 if the intid has non-maskable property. And for ICC_NMIAR1_EL1 register, it should return 1023 if the intid do not have non-maskable property. Howerever, these are not necessary for ICC_HPPIR1_EL1 register. And the APR and RPR has NMI bits which should be handled correctly. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [PMM: Separate out whether cpuif supports NMI from whether the GIC proper (IRI) supports NMI] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-19-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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4 changed files with 155 additions and 5 deletions
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@ -225,6 +225,13 @@ struct GICv3CPUState {
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/* This is temporary working state, to avoid a malloc in gicv3_update() */
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bool seenbetter;
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/*
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* Whether the CPU interface has NMI support (FEAT_GICv3_NMI). The
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* CPU interface may support NMIs even when the GIC proper (what the
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* spec calls the IRI; the redistributors and distributor) does not.
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*/
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bool nmi_support;
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};
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/*
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