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hw: timer: ibex_timer: Fixup reading w/o register
This change fixes a bug where a write only register is read. As per https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table the 'INTR_TEST0' register is write only. Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220110051606.4031241-1-alistair.francis@opensource.wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2 changed files with 5 additions and 10 deletions
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@ -43,7 +43,6 @@ struct IbexTimerState {
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uint32_t timer_compare_upper0;
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uint32_t timer_intr_enable;
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uint32_t timer_intr_state;
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uint32_t timer_intr_test;
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uint32_t timebase_freq;
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