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aspeed: add support for the Aspeed MII controller of the AST2600

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The AST2600 SoC has an extra controller to set the PHY registers.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190925143248.10000-23-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Cédric Le Goater 2019-09-25 16:32:47 +02:00 • committed by Peter Maydell
parent d300db0277
commit 289251b033
4 changed files with 204 additions and 0 deletions
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5
include/hw/arm/aspeed_soc.h
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@ -52,6 +52,7 @@ typedef struct AspeedSoCState {
AspeedSDMCState sdmc;
AspeedWDTState wdt[ASPEED_WDTS_NUM];
FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
AspeedMiiState mii[ASPEED_MACS_NUM];
AspeedGPIOState gpio;
AspeedGPIOState gpio_1_8v;
AspeedSDHCIState sdhci;
@ -117,6 +118,10 @@ enum {
ASPEED_ETH2,
ASPEED_ETH3,
ASPEED_ETH4,
ASPEED_MII1,
ASPEED_MII2,
ASPEED_MII3,
ASPEED_MII4,
ASPEED_SDRAM,
ASPEED_XDMA,
};