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target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
mstatus/mstatush and vsstatus/vsstatush are two halved for RISCV32. This patch expands mstatus and vsstatus to uint64_t instead of target_ulong so that it can be saved as one unit and reduce some ifdefs in the code. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201026115530.304-2-jiangyifei@huawei.com
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4e1e3003fb
commit
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6 changed files with 41 additions and 74 deletions
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@ -110,27 +110,19 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
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void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
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{
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target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
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MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE;
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uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
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MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
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MSTATUS64_UXL;
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bool current_virt = riscv_cpu_virt_enabled(env);
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g_assert(riscv_has_ext(env, RVH));
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#if defined(TARGET_RISCV64)
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mstatus_mask |= MSTATUS64_UXL;
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#endif
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if (current_virt) {
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/* Current V=1 and we are about to change to V=0 */
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env->vsstatus = env->mstatus & mstatus_mask;
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env->mstatus &= ~mstatus_mask;
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env->mstatus |= env->mstatus_hs;
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#if defined(TARGET_RISCV32)
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env->vsstatush = env->mstatush;
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env->mstatush |= env->mstatush_hs;
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#endif
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env->vstvec = env->stvec;
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env->stvec = env->stvec_hs;
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@ -154,11 +146,6 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
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env->mstatus &= ~mstatus_mask;
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env->mstatus |= env->vsstatus;
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#if defined(TARGET_RISCV32)
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env->mstatush_hs = env->mstatush;
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env->mstatush |= env->vsstatush;
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#endif
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env->stvec_hs = env->stvec;
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env->stvec = env->vstvec;
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@ -727,7 +714,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
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access_type != MMU_INST_FETCH &&
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get_field(env->mstatus, MSTATUS_MPRV) &&
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MSTATUS_MPV_ISSET(env)) {
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get_field(env->mstatus, MSTATUS_MPV)) {
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riscv_cpu_set_two_stage_lookup(env, true);
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}
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@ -799,7 +786,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
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access_type != MMU_INST_FETCH &&
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get_field(env->mstatus, MSTATUS_MPRV) &&
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MSTATUS_MPV_ISSET(env)) {
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get_field(env->mstatus, MSTATUS_MPV)) {
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riscv_cpu_set_two_stage_lookup(env, false);
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}
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@ -862,7 +849,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env);
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target_ulong s;
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uint64_t s;
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/* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
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* so we mask off the MSB and separate into trap type and cause.
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@ -995,19 +982,11 @@ void riscv_cpu_do_interrupt(CPUState *cs)
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if (riscv_cpu_virt_enabled(env)) {
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riscv_cpu_swap_hypervisor_regs(env);
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}
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#ifdef TARGET_RISCV32
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env->mstatush = set_field(env->mstatush, MSTATUS_MPV,
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riscv_cpu_virt_enabled(env));
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if (riscv_cpu_virt_enabled(env) && tval) {
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env->mstatush = set_field(env->mstatush, MSTATUS_GVA, 1);
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}
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#else
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env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
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riscv_cpu_virt_enabled(env));
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riscv_cpu_virt_enabled(env));
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if (riscv_cpu_virt_enabled(env) && tval) {
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env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
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}
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#endif
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mtval2 = env->guest_phys_fault_addr;
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