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target/mips: Replace MO_TE by mo_endian()

Browse source 
Replace compile-time MO_TE evaluation by runtime mo_endian() one,
which expand target endianness from DisasContext.

Mechanical change using:

  $ sed -i -e 's/MO_TE/mo_endian(ctx)/' \
     $(git grep -l MO_TE target/mips)

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241010215015.44326-11-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2024-09-26 18:43:19 +02:00
parent 96ccd8534f
commit 2803e24694
6 changed files with 106 additions and 103 deletions
Download patch file Download diff file Expand all files Collapse all files

22
target/mips/tcg/micromips_translate.c.inc
View file

@ -977,23 +977,23 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);
return; return;
} }
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL | tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd); gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 4); tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL | tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd + 1); gen_store_gpr(t1, rd + 1);
break; break;
case SWP: case SWP:
gen_load_gpr(t1, rd); gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
tcg_gen_movi_tl(t1, 4); tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
gen_load_gpr(t1, rd + 1); gen_load_gpr(t1, rd + 1);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
break; break;
#ifdef TARGET_MIPS64 #ifdef TARGET_MIPS64
@ -1002,23 +1002,23 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);
return; return;
} }
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd); gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 8); tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd + 1); gen_store_gpr(t1, rd + 1);
break; break;
case SDP: case SDP:
gen_load_gpr(t1, rd); gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
tcg_gen_movi_tl(t1, 8); tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
gen_load_gpr(t1, rd + 1); gen_load_gpr(t1, rd + 1);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
break; break;
#endif #endif
@ -2572,13 +2572,13 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
gen_st(ctx, mips32_op, rt, rs, offset); gen_st(ctx, mips32_op, rt, rs, offset);
break; break;
case SC: case SC:
gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_SL, false); gen_st_cond(ctx, rt, rs, offset, mo_endian(ctx) | MO_SL, false);
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case SCD: case SCD:
check_insn(ctx, ISA_MIPS3); check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx); check_mips_64(ctx);
gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_UQ, false); gen_st_cond(ctx, rt, rs, offset, mo_endian(ctx) | MO_UQ, false);
break; break;
#endif #endif
case LD_EVA: case LD_EVA:
@ -2659,7 +2659,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
mips32_op = OPC_SHE; mips32_op = OPC_SHE;
goto do_st_lr; goto do_st_lr;
case SCE: case SCE:
gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_SL, true); gen_st_cond(ctx, rt, rs, offset, mo_endian(ctx) | MO_SL, true);
break; break;
case SWE: case SWE:
mips32_op = OPC_SWE; mips32_op = OPC_SWE;

12
target/mips/tcg/mips16e_translate.c.inc
View file

@ -135,7 +135,7 @@ static void decr_and_store(DisasContext *ctx, unsigned regidx, TCGv t0)
tcg_gen_movi_tl(t2, -4); tcg_gen_movi_tl(t2, -4);
gen_op_addr_add(ctx, t0, t0, t2); gen_op_addr_add(ctx, t0, t0, t2);
gen_load_gpr(t1, regidx); gen_load_gpr(t1, regidx);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
} }
@ -184,25 +184,25 @@ static void gen_mips16_save(DisasContext *ctx,
case 4: case 4:
gen_base_offset_addr(ctx, t0, 29, 12); gen_base_offset_addr(ctx, t0, 29, 12);
gen_load_gpr(t1, 7); gen_load_gpr(t1, 7);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
/* Fall through */ /* Fall through */
case 3: case 3:
gen_base_offset_addr(ctx, t0, 29, 8); gen_base_offset_addr(ctx, t0, 29, 8);
gen_load_gpr(t1, 6); gen_load_gpr(t1, 6);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
/* Fall through */ /* Fall through */
case 2: case 2:
gen_base_offset_addr(ctx, t0, 29, 4); gen_base_offset_addr(ctx, t0, 29, 4);
gen_load_gpr(t1, 5); gen_load_gpr(t1, 5);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
/* Fall through */ /* Fall through */
case 1: case 1:
gen_base_offset_addr(ctx, t0, 29, 0); gen_base_offset_addr(ctx, t0, 29, 0);
gen_load_gpr(t1, 4); gen_load_gpr(t1, 4);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
} }
@ -297,7 +297,7 @@ static void decr_and_load(DisasContext *ctx, unsigned regidx, TCGv t0)
tcg_gen_movi_tl(t2, -4); tcg_gen_movi_tl(t2, -4);
gen_op_addr_add(ctx, t0, t0, t2); gen_op_addr_add(ctx, t0, t0, t2);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_gpr(t1, regidx); gen_store_gpr(t1, regidx);
} }

10
target/mips/tcg/mxu_translate.c
View file

@ -4803,19 +4803,19 @@ static void decode_opc_mxu__pool17(DisasContext *ctx)
switch (opcode) { switch (opcode) {
case OPC_MXU_LXW: case OPC_MXU_LXW:
gen_mxu_lxx(ctx, strd2, MO_TE | MO_UL); gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_UL);
break; break;
case OPC_MXU_LXB: case OPC_MXU_LXB:
gen_mxu_lxx(ctx, strd2, MO_TE | MO_SB); gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_SB);
break; break;
case OPC_MXU_LXH: case OPC_MXU_LXH:
gen_mxu_lxx(ctx, strd2, MO_TE | MO_SW); gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_SW);
break; break;
case OPC_MXU_LXBU: case OPC_MXU_LXBU:
gen_mxu_lxx(ctx, strd2, MO_TE | MO_UB); gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_UB);
break; break;
case OPC_MXU_LXHU: case OPC_MXU_LXHU:
gen_mxu_lxx(ctx, strd2, MO_TE | MO_UW); gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_UW);
break; break;
default: default:
MIPS_INVAL("decode_opc_mxu"); MIPS_INVAL("decode_opc_mxu");

37
target/mips/tcg/nanomips_translate.c.inc
View file

@ -998,7 +998,8 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
TCGv tmp2 = tcg_temp_new(); TCGv tmp2 = tcg_temp_new();
gen_base_offset_addr(ctx, taddr, base, offset); gen_base_offset_addr(ctx, taddr, base, offset);
tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TE | MO_UQ | MO_ALIGN); tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx,
mo_endian(ctx) | MO_UQ | MO_ALIGN);
if (disas_is_bigendian(ctx)) { if (disas_is_bigendian(ctx)) {
tcg_gen_extr_i64_tl(tmp2, tmp1, tval); tcg_gen_extr_i64_tl(tmp2, tmp1, tval);
} else { } else {
@ -1075,7 +1076,7 @@ static void gen_save(DisasContext *ctx, uint8_t rt, uint8_t count,
gen_base_offset_addr(ctx, va, 29, this_offset); gen_base_offset_addr(ctx, va, 29, this_offset);
gen_load_gpr(t0, this_rt); gen_load_gpr(t0, this_rt);
tcg_gen_qemu_st_tl(t0, va, ctx->mem_idx, tcg_gen_qemu_st_tl(t0, va, ctx->mem_idx,
MO_TE | MO_UL | ctx->default_tcg_memop_mask); mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask);
counter++; counter++;
} }
@ -1095,8 +1096,8 @@ static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count,
int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f); int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f);
int this_offset = u - ((counter + 1) << 2); int this_offset = u - ((counter + 1) << 2);
gen_base_offset_addr(ctx, va, 29, this_offset); gen_base_offset_addr(ctx, va, 29, this_offset);
tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TE | MO_SL | tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx,
ctx->default_tcg_memop_mask); mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask);
tcg_gen_ext32s_tl(t0, t0); tcg_gen_ext32s_tl(t0, t0);
gen_store_gpr(t0, this_rt); gen_store_gpr(t0, this_rt);
counter++; counter++;
@ -2647,13 +2648,13 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
case NM_LHX: case NM_LHX:
/*case NM_LHXS:*/ /*case NM_LHXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
MO_TE | MO_SW | ctx->default_tcg_memop_mask); mo_endian(ctx) | MO_SW | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd); gen_store_gpr(t0, rd);
break; break;
case NM_LWX: case NM_LWX:
/*case NM_LWXS:*/ /*case NM_LWXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
MO_TE | MO_SL | ctx->default_tcg_memop_mask); mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd); gen_store_gpr(t0, rd);
break; break;
case NM_LBUX: case NM_LBUX:
@ -2663,7 +2664,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
case NM_LHUX: case NM_LHUX:
/*case NM_LHUXS:*/ /*case NM_LHUXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
MO_TE | MO_UW | ctx->default_tcg_memop_mask); mo_endian(ctx) | MO_UW | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd); gen_store_gpr(t0, rd);
break; break;
case NM_SBX: case NM_SBX:
@ -2676,14 +2677,14 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
check_nms(ctx); check_nms(ctx);
gen_load_gpr(t1, rd); gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
MO_TE | MO_UW | ctx->default_tcg_memop_mask); mo_endian(ctx) | MO_UW | ctx->default_tcg_memop_mask);
break; break;
case NM_SWX: case NM_SWX:
/*case NM_SWXS:*/ /*case NM_SWXS:*/
check_nms(ctx); check_nms(ctx);
gen_load_gpr(t1, rd); gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
MO_TE | MO_UL | ctx->default_tcg_memop_mask); mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask);
break; break;
case NM_LWC1X: case NM_LWC1X:
/*case NM_LWC1XS:*/ /*case NM_LWC1XS:*/
@ -3737,7 +3738,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
tcg_gen_movi_tl(t0, addr); tcg_gen_movi_tl(t0, addr);
tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx,
MO_TE | MO_SL mo_endian(ctx) | MO_SL
| ctx->default_tcg_memop_mask); | ctx->default_tcg_memop_mask);
} }
break; break;
@ -3755,7 +3756,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t1, rt); gen_load_gpr(t1, rt);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
MO_TE | MO_UL mo_endian(ctx) | MO_UL
| ctx->default_tcg_memop_mask); | ctx->default_tcg_memop_mask);
} }
break; break;
@ -4135,13 +4136,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
switch (extract32(ctx->opcode, 11, 4)) { switch (extract32(ctx->opcode, 11, 4)) {
case NM_UALH: case NM_UALH:
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
MO_TE | MO_SW | MO_UNALN); mo_endian(ctx) | MO_SW | MO_UNALN);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
break; break;
case NM_UASH: case NM_UASH:
gen_load_gpr(t1, rt); gen_load_gpr(t1, rt);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
MO_TE | MO_UW | MO_UNALN); mo_endian(ctx) | MO_UW | MO_UNALN);
break; break;
} }
} }
@ -4163,7 +4164,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
case NM_P_SC: case NM_P_SC:
switch (ctx->opcode & 0x03) { switch (ctx->opcode & 0x03) {
case NM_SC: case NM_SC:
gen_st_cond(ctx, rt, rs, s, MO_TE | MO_SL, false); gen_st_cond(ctx, rt, rs, s, mo_endian(ctx) | MO_SL,
false);
break; break;
case NM_SCWP: case NM_SCWP:
check_xnp(ctx); check_xnp(ctx);
@ -4276,7 +4278,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
check_xnp(ctx); check_xnp(ctx);
check_eva(ctx); check_eva(ctx);
check_cp0_enabled(ctx); check_cp0_enabled(ctx);
gen_st_cond(ctx, rt, rs, s, MO_TE | MO_SL, true); gen_st_cond(ctx, rt, rs, s, mo_endian(ctx) | MO_SL,
true);
break; break;
case NM_SCWPE: case NM_SCWPE:
check_xnp(ctx); check_xnp(ctx);
@ -4319,7 +4322,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
switch (extract32(ctx->opcode, 11, 1)) { switch (extract32(ctx->opcode, 11, 1)) {
case NM_LWM: case NM_LWM:
tcg_gen_qemu_ld_tl(t1, va, ctx->mem_idx, tcg_gen_qemu_ld_tl(t1, va, ctx->mem_idx,
memop | MO_TE | MO_SL); memop | mo_endian(ctx) | MO_SL);
gen_store_gpr(t1, this_rt); gen_store_gpr(t1, this_rt);
if ((this_rt == rs) && if ((this_rt == rs) &&
(counter != (count - 1))) { (counter != (count - 1))) {
@ -4330,7 +4333,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
this_rt = (rt == 0) ? 0 : this_rt; this_rt = (rt == 0) ? 0 : this_rt;
gen_load_gpr(t1, this_rt); gen_load_gpr(t1, this_rt);
tcg_gen_qemu_st_tl(t1, va, ctx->mem_idx, tcg_gen_qemu_st_tl(t1, va, ctx->mem_idx,
memop | MO_TE | MO_UL); memop | mo_endian(ctx) | MO_UL);
break; break;
} }
counter++; counter++;

120
target/mips/tcg/translate.c
View file

@ -1964,9 +1964,9 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); \ gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); \
} }
#endif #endif
OP_LD_ATOMIC(ll, MO_TE | MO_SL); OP_LD_ATOMIC(ll, mo_endian(ctx) | MO_SL);
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
OP_LD_ATOMIC(lld, MO_TE | MO_UQ); OP_LD_ATOMIC(lld, mo_endian(ctx) | MO_UQ);
#endif #endif
#undef OP_LD_ATOMIC #undef OP_LD_ATOMIC
@ -2073,12 +2073,12 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
switch (opc) { switch (opc) {
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_LWU: case OPC_LWU:
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UL | tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
break; break;
case OPC_LD: case OPC_LD:
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
break; break;
@ -2090,33 +2090,33 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
case OPC_LDL: case OPC_LDL:
t1 = tcg_temp_new(); t1 = tcg_temp_new();
gen_load_gpr(t1, rt); gen_load_gpr(t1, rt);
gen_lxl(ctx, t1, t0, mem_idx, MO_TE | MO_UQ); gen_lxl(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr(t1, rt); gen_store_gpr(t1, rt);
break; break;
case OPC_LDR: case OPC_LDR:
t1 = tcg_temp_new(); t1 = tcg_temp_new();
gen_load_gpr(t1, rt); gen_load_gpr(t1, rt);
gen_lxr(ctx, t1, t0, mem_idx, MO_TE | MO_UQ); gen_lxr(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr(t1, rt); gen_store_gpr(t1, rt);
break; break;
case OPC_LDPC: case OPC_LDPC:
t1 = tcg_constant_tl(pc_relative_pc(ctx)); t1 = tcg_constant_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UQ); tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
break; break;
#endif #endif
case OPC_LWPC: case OPC_LWPC:
t1 = tcg_constant_tl(pc_relative_pc(ctx)); t1 = tcg_constant_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SL); tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SL);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
break; break;
case OPC_LWE: case OPC_LWE:
mem_idx = MIPS_HFLAG_UM; mem_idx = MIPS_HFLAG_UM;
/* fall through */ /* fall through */
case OPC_LW: case OPC_LW:
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SL | tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
break; break;
@ -2124,7 +2124,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
mem_idx = MIPS_HFLAG_UM; mem_idx = MIPS_HFLAG_UM;
/* fall through */ /* fall through */
case OPC_LH: case OPC_LH:
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SW | tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SW |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
break; break;
@ -2132,7 +2132,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
mem_idx = MIPS_HFLAG_UM; mem_idx = MIPS_HFLAG_UM;
/* fall through */ /* fall through */
case OPC_LHU: case OPC_LHU:
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UW | tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UW |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
break; break;
@ -2156,7 +2156,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
case OPC_LWL: case OPC_LWL:
t1 = tcg_temp_new(); t1 = tcg_temp_new();
gen_load_gpr(t1, rt); gen_load_gpr(t1, rt);
gen_lxl(ctx, t1, t0, mem_idx, MO_TE | MO_UL); gen_lxl(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UL);
tcg_gen_ext32s_tl(t1, t1); tcg_gen_ext32s_tl(t1, t1);
gen_store_gpr(t1, rt); gen_store_gpr(t1, rt);
break; break;
@ -2166,7 +2166,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
case OPC_LWR: case OPC_LWR:
t1 = tcg_temp_new(); t1 = tcg_temp_new();
gen_load_gpr(t1, rt); gen_load_gpr(t1, rt);
gen_lxr(ctx, t1, t0, mem_idx, MO_TE | MO_UL); gen_lxr(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UL);
tcg_gen_ext32s_tl(t1, t1); tcg_gen_ext32s_tl(t1, t1);
gen_store_gpr(t1, rt); gen_store_gpr(t1, rt);
break; break;
@ -2194,7 +2194,7 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt,
switch (opc) { switch (opc) {
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_SD: case OPC_SD:
tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
break; break;
case OPC_SDL: case OPC_SDL:
@ -2208,14 +2208,14 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt,
mem_idx = MIPS_HFLAG_UM; mem_idx = MIPS_HFLAG_UM;
/* fall through */ /* fall through */
case OPC_SW: case OPC_SW:
tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UL | tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
break; break;
case OPC_SHE: case OPC_SHE:
mem_idx = MIPS_HFLAG_UM; mem_idx = MIPS_HFLAG_UM;
/* fall through */ /* fall through */
case OPC_SH: case OPC_SH:
tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UW | tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UW |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
break; break;
case OPC_SBE: case OPC_SBE:
@ -2281,7 +2281,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
case OPC_LWC1: case OPC_LWC1:
{ {
TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp0 = tcg_temp_new_i32();
tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_SL | tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_fpr32(ctx, fp0, ft); gen_store_fpr32(ctx, fp0, ft);
} }
@ -2290,14 +2290,14 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
{ {
TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, ft); gen_load_fpr32(ctx, fp0, ft);
tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL | tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
} }
break; break;
case OPC_LDC1: case OPC_LDC1:
{ {
TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp0 = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_fpr64(ctx, fp0, ft); gen_store_fpr64(ctx, fp0, ft);
} }
@ -2306,7 +2306,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
{ {
TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, ft); gen_load_fpr64(ctx, fp0, ft);
tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
} }
break; break;
@ -2987,14 +2987,14 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
case R6_OPC_LWPC: case R6_OPC_LWPC:
offset = sextract32(ctx->opcode << 2, 0, 21); offset = sextract32(ctx->opcode << 2, 0, 21);
addr = addr_add(ctx, pc, offset); addr = addr_add(ctx, pc, offset);
gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_SL); gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_SL);
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_LWUPC: case OPC_LWUPC:
check_mips_64(ctx); check_mips_64(ctx);
offset = sextract32(ctx->opcode << 2, 0, 21); offset = sextract32(ctx->opcode << 2, 0, 21);
addr = addr_add(ctx, pc, offset); addr = addr_add(ctx, pc, offset);
gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_UL); gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UL);
break; break;
#endif #endif
default: default:
@ -3021,7 +3021,7 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
check_mips_64(ctx); check_mips_64(ctx);
offset = sextract32(ctx->opcode << 3, 0, 21); offset = sextract32(ctx->opcode << 3, 0, 21);
addr = addr_add(ctx, (pc & ~0x7), offset); addr = addr_add(ctx, (pc & ~0x7), offset);
gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_UQ); gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
break; break;
#endif #endif
default: default:
@ -4160,10 +4160,10 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
case OPC_GSLQ: case OPC_GSLQ:
t1 = tcg_temp_new(); t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset); gen_base_offset_addr(ctx, t0, rs, lsq_offset);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rt); gen_store_gpr(t1, rt);
gen_store_gpr(t0, lsq_rt1); gen_store_gpr(t0, lsq_rt1);
@ -4172,10 +4172,10 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
check_cp1_enabled(ctx); check_cp1_enabled(ctx);
t1 = tcg_temp_new(); t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset); gen_base_offset_addr(ctx, t0, rs, lsq_offset);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_fpr64(ctx, t1, rt); gen_store_fpr64(ctx, t1, rt);
gen_store_fpr64(ctx, t0, lsq_rt1); gen_store_fpr64(ctx, t0, lsq_rt1);
@ -4184,11 +4184,11 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
t1 = tcg_temp_new(); t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset); gen_base_offset_addr(ctx, t0, rs, lsq_offset);
gen_load_gpr(t1, rt); gen_load_gpr(t1, rt);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
gen_load_gpr(t1, lsq_rt1); gen_load_gpr(t1, lsq_rt1);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
break; break;
case OPC_GSSQC1: case OPC_GSSQC1:
@ -4196,11 +4196,11 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
t1 = tcg_temp_new(); t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset); gen_base_offset_addr(ctx, t0, rs, lsq_offset);
gen_load_fpr64(ctx, t1, rt); gen_load_fpr64(ctx, t1, rt);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
gen_load_fpr64(ctx, t1, lsq_rt1); gen_load_fpr64(ctx, t1, lsq_rt1);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
break; break;
#endif #endif
@ -4213,7 +4213,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_load_fpr32(ctx, fp0, rt); gen_load_fpr32(ctx, fp0, rt);
t1 = tcg_temp_new(); t1 = tcg_temp_new();
tcg_gen_ext_i32_tl(t1, fp0); tcg_gen_ext_i32_tl(t1, fp0);
gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UL); gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL);
tcg_gen_trunc_tl_i32(fp0, t1); tcg_gen_trunc_tl_i32(fp0, t1);
gen_store_fpr32(ctx, fp0, rt); gen_store_fpr32(ctx, fp0, rt);
break; break;
@ -4224,7 +4224,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_load_fpr32(ctx, fp0, rt); gen_load_fpr32(ctx, fp0, rt);
t1 = tcg_temp_new(); t1 = tcg_temp_new();
tcg_gen_ext_i32_tl(t1, fp0); tcg_gen_ext_i32_tl(t1, fp0);
gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UL); gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL);
tcg_gen_trunc_tl_i32(fp0, t1); tcg_gen_trunc_tl_i32(fp0, t1);
gen_store_fpr32(ctx, fp0, rt); gen_store_fpr32(ctx, fp0, rt);
break; break;
@ -4234,7 +4234,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_base_offset_addr(ctx, t0, rs, shf_offset); gen_base_offset_addr(ctx, t0, rs, shf_offset);
t1 = tcg_temp_new(); t1 = tcg_temp_new();
gen_load_fpr64(ctx, t1, rt); gen_load_fpr64(ctx, t1, rt);
gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UQ); gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_fpr64(ctx, t1, rt); gen_store_fpr64(ctx, t1, rt);
break; break;
case OPC_GSLDRC1: case OPC_GSLDRC1:
@ -4242,7 +4242,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_base_offset_addr(ctx, t0, rs, shf_offset); gen_base_offset_addr(ctx, t0, rs, shf_offset);
t1 = tcg_temp_new(); t1 = tcg_temp_new();
gen_load_fpr64(ctx, t1, rt); gen_load_fpr64(ctx, t1, rt);
gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UQ); gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_fpr64(ctx, t1, rt); gen_store_fpr64(ctx, t1, rt);
break; break;
#endif #endif
@ -4360,7 +4360,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
break; break;
case OPC_GSLHX: case OPC_GSLHX:
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW | tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
break; break;
@ -4369,7 +4369,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
if (rd) { if (rd) {
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
} }
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL | tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
break; break;
@ -4379,7 +4379,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
if (rd) { if (rd) {
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
} }
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
break; break;
@ -4390,7 +4390,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
} }
fp0 = tcg_temp_new_i32(); fp0 = tcg_temp_new_i32();
tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_SL | tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_fpr32(ctx, fp0, rt); gen_store_fpr32(ctx, fp0, rt);
break; break;
@ -4400,7 +4400,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
if (rd) { if (rd) {
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
} }
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
gen_store_fpr64(ctx, t0, rt); gen_store_fpr64(ctx, t0, rt);
break; break;
@ -4413,34 +4413,34 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
case OPC_GSSHX: case OPC_GSSHX:
t1 = tcg_temp_new(); t1 = tcg_temp_new();
gen_load_gpr(t1, rt); gen_load_gpr(t1, rt);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UW | tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UW |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
break; break;
case OPC_GSSWX: case OPC_GSSWX:
t1 = tcg_temp_new(); t1 = tcg_temp_new();
gen_load_gpr(t1, rt); gen_load_gpr(t1, rt);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_GSSDX: case OPC_GSSDX:
t1 = tcg_temp_new(); t1 = tcg_temp_new();
gen_load_gpr(t1, rt); gen_load_gpr(t1, rt);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
break; break;
#endif #endif
case OPC_GSSWXC1: case OPC_GSSWXC1:
fp0 = tcg_temp_new_i32(); fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, rt); gen_load_fpr32(ctx, fp0, rt);
tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL | tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_GSSDXC1: case OPC_GSSDXC1:
t1 = tcg_temp_new(); t1 = tcg_temp_new();
gen_load_fpr64(ctx, t1, rt); gen_load_fpr64(ctx, t1, rt);
tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask); ctx->default_tcg_memop_mask);
break; break;
#endif #endif
@ -10779,7 +10779,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{ {
TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp0 = tcg_temp_new_i32();
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL); tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL);
tcg_gen_trunc_tl_i32(fp0, t0); tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32(ctx, fp0, fd); gen_store_fpr32(ctx, fp0, fd);
} }
@ -10789,7 +10789,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
check_cp1_registers(ctx, fd); check_cp1_registers(ctx, fd);
{ {
TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp0 = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_fpr64(ctx, fp0, fd); gen_store_fpr64(ctx, fp0, fd);
} }
break; break;
@ -10799,7 +10799,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{ {
TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp0 = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_fpr64(ctx, fp0, fd); gen_store_fpr64(ctx, fp0, fd);
} }
break; break;
@ -10808,7 +10808,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{ {
TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp0, fs);
tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL); tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL);
} }
break; break;
case OPC_SDXC1: case OPC_SDXC1:
@ -10817,7 +10817,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{ {
TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp0, fs);
tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
} }
break; break;
case OPC_SUXC1: case OPC_SUXC1:
@ -10826,7 +10826,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{ {
TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp0, fs);
tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
} }
break; break;
} }
@ -11476,7 +11476,7 @@ void gen_ldxs(DisasContext *ctx, int base, int index, int rd)
gen_op_addr_add(ctx, t0, t1, t0); gen_op_addr_add(ctx, t0, t1, t0);
} }
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL);
gen_store_gpr(t1, rd); gen_store_gpr(t1, rd);
} }
@ -11567,16 +11567,16 @@ static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
gen_store_gpr(t0, rd); gen_store_gpr(t0, rd);
break; break;
case OPC_LHX: case OPC_LHX:
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW); tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW);
gen_store_gpr(t0, rd); gen_store_gpr(t0, rd);
break; break;
case OPC_LWX: case OPC_LWX:
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL); tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL);
gen_store_gpr(t0, rd); gen_store_gpr(t0, rd);
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_LDX: case OPC_LDX:
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ); tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr(t0, rd); gen_store_gpr(t0, rd);
break; break;
#endif #endif
@ -13719,7 +13719,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
} }
break; break;
case R6_OPC_SC: case R6_OPC_SC:
gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, false); gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, false);
break; break;
case R6_OPC_LL: case R6_OPC_LL:
gen_ld(ctx, op1, rt, rs, imm); gen_ld(ctx, op1, rt, rs, imm);
@ -13765,7 +13765,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
#endif #endif
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case R6_OPC_SCD: case R6_OPC_SCD:
gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_UQ, false); gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_UQ, false);
break; break;
case R6_OPC_LLD: case R6_OPC_LLD:
gen_ld(ctx, op1, rt, rs, imm); gen_ld(ctx, op1, rt, rs, imm);
@ -14448,7 +14448,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
return; return;
case OPC_SCE: case OPC_SCE:
check_cp0_enabled(ctx); check_cp0_enabled(ctx);
gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, true); gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, true);
return; return;
case OPC_CACHEE: case OPC_CACHEE:
check_eva(ctx); check_eva(ctx);
@ -14912,7 +14912,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
if (ctx->insn_flags & INSN_R5900) { if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900); check_insn_opc_user_only(ctx, INSN_R5900);
} }
gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, false); gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, false);
break; break;
case OPC_CACHE: case OPC_CACHE:
check_cp0_enabled(ctx); check_cp0_enabled(ctx);
@ -15191,7 +15191,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
check_insn_opc_user_only(ctx, INSN_R5900); check_insn_opc_user_only(ctx, INSN_R5900);
} }
check_mips_64(ctx); check_mips_64(ctx);
gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_UQ, false); gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_UQ, false);
break; break;
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */ case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */
if (ctx->insn_flags & ISA_MIPS_R6) { if (ctx->insn_flags & ISA_MIPS_R6) {

8
target/mips/tcg/tx79_translate.c
View file

@ -340,12 +340,12 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a)
tcg_gen_andi_tl(addr, addr, ~0xf); tcg_gen_andi_tl(addr, addr, ~0xf);
/* Lower half */ /* Lower half */
tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr(t0, a->rt); gen_store_gpr(t0, a->rt);
/* Upper half */ /* Upper half */
tcg_gen_addi_i64(addr, addr, 8); tcg_gen_addi_i64(addr, addr, 8);
tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr_hi(t0, a->rt); gen_store_gpr_hi(t0, a->rt);
return true; return true;
} }
@ -364,12 +364,12 @@ static bool trans_SQ(DisasContext *ctx, arg_i *a)
/* Lower half */ /* Lower half */
gen_load_gpr(t0, a->rt); gen_load_gpr(t0, a->rt);
tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
/* Upper half */ /* Upper half */
tcg_gen_addi_i64(addr, addr, 8); tcg_gen_addi_i64(addr, addr, 8);
gen_load_gpr_hi(t0, a->rt); gen_load_gpr_hi(t0, a->rt);
tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
return true; return true;
} }