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hw/loongarch/virt: Add kernel irqchip support
If kvm_irqchip_in_kernel() return true, interrupt controller ExtIOI, IPI, PCH_PCI and PCH_MSI should be emlated in kernel. And it is not necessary to create memory region for these devices in user space. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250606063607.2557540-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
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27f5d500c2
3 changed files with 50 additions and 24 deletions
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@ -414,12 +414,6 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
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lvms->ipi = ipi;
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sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
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/* IPI iocsr memory region */
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memory_region_add_subregion(&lvms->system_iocsr, SMP_IPI_MAILBOX,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0));
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memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1));
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/* Create EXTIOI device */
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extioi = qdev_new(TYPE_LOONGARCH_EXTIOI);
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lvms->extioi = extioi;
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@ -427,12 +421,6 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
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qdev_prop_set_bit(extioi, "has-virtualization-extension", true);
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}
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sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal);
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memory_region_add_subregion(&lvms->system_iocsr, APIC_BASE,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0));
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if (virt_is_veiointc_enabled(lvms)) {
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memory_region_add_subregion(&lvms->system_iocsr, EXTIOI_VIRT_BASE,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 1));
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}
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virt_cpu_irq_init(lvms);
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pch_pic = qdev_new(TYPE_LOONGARCH_PIC);
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@ -440,13 +428,6 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
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qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
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d = SYS_BUS_DEVICE(pch_pic);
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sysbus_realize_and_unref(d, &error_fatal);
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memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE,
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sysbus_mmio_get_region(d, 0));
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/* Connect pch_pic irqs to extioi */
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for (i = 0; i < num; i++) {
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qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
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}
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pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
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start = num;
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@ -456,12 +437,40 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
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d = SYS_BUS_DEVICE(pch_msi);
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sysbus_realize_and_unref(d, &error_fatal);
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sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW);
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for (i = 0; i < num; i++) {
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/* Connect pch_msi irqs to extioi */
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qdev_connect_gpio_out(DEVICE(d), i,
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qdev_get_gpio_in(extioi, i + start));
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}
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if (kvm_irqchip_in_kernel()) {
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kvm_loongarch_init_irq_routing();
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} else {
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/* IPI iocsr memory region */
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memory_region_add_subregion(&lvms->system_iocsr, SMP_IPI_MAILBOX,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0));
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memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1));
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/* EXTIOI iocsr memory region */
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memory_region_add_subregion(&lvms->system_iocsr, APIC_BASE,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0));
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if (virt_is_veiointc_enabled(lvms)) {
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memory_region_add_subregion(&lvms->system_iocsr, EXTIOI_VIRT_BASE,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 1));
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}
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/* PCH_PIC memory region */
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memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(pch_pic), 0));
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/* Connect pch_pic irqs to extioi */
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for (i = 0; i < VIRT_PCH_PIC_IRQ_NUM; i++) {
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qdev_connect_gpio_out(DEVICE(pch_pic), i,
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qdev_get_gpio_in(extioi, i));
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}
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for (i = VIRT_PCH_PIC_IRQ_NUM; i < EXTIOI_IRQS; i++) {
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/* Connect pch_msi irqs to extioi */
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qdev_connect_gpio_out(DEVICE(pch_msi), i - VIRT_PCH_PIC_IRQ_NUM,
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qdev_get_gpio_in(extioi, i));
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}
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}
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virt_devices_init(pch_pic, lvms);
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}
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@ -503,5 +503,6 @@ static inline void kvm_loongarch_cpu_post_init(LoongArchCPU *cpu)
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{
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}
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#endif
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void kvm_loongarch_init_irq_routing(void);
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#endif /* LOONGARCH_CPU_H */
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@ -1240,6 +1240,22 @@ void kvm_arch_init_irq_routing(KVMState *s)
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{
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}
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void kvm_loongarch_init_irq_routing(void)
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{
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int i;
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kvm_async_interrupts_allowed = true;
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kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
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if (kvm_has_gsi_routing()) {
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for (i = 0; i < KVM_IRQCHIP_NUM_PINS; ++i) {
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kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
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}
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kvm_gsi_routing_allowed = true;
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kvm_irqchip_commit_routes(kvm_state);
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}
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}
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int kvm_arch_get_default_type(MachineState *ms)
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{
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return 0;
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