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tcg: Convert shl to TCGOutOpBinary

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-07 21:33:33 -08:00
parent cd9acd2049
commit 27d21ee7c7
11 changed files with 241 additions and 124 deletions
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25
tcg/arm/tcg-target.c.inc
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@ -1963,6 +1963,25 @@ static const TCGOutOpBinary outop_remu = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_shl(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_LSL(a2));
}
static void tgen_shli(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, tcg_target_long a2)
{
tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1,
SHIFT_IMM_LSL(a2 & 0x1f));
}
static const TCGOutOpBinary outop_shl = {
.base.static_constraint = C_O1_I2(r, r, ri),
.out_rrr = tgen_shl,
.out_rri = tgen_shli,
};
static void tgen_sub(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
@ -2114,11 +2133,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
case INDEX_op_muls2_i32:
tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]);
break;
/* XXX: Perhaps args[2] & 0x1f is wrong */
case INDEX_op_shl_i32:
c = const_args[2] ?
SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
goto gen_shift32;
case INDEX_op_shr_i32:
c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
@ -2300,7 +2314,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_muls2_i32:
return C_O2_I2(r, r, r, r);
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
case INDEX_op_sar_i32:
case INDEX_op_rotl_i32: