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hpet: Coding style cleanups and some refactorings

Browse source 
This moves the private HPET structures into the C module, simplifies
some helper functions and fixes most coding style issues (biggest chunk
was improper switch-case indention). No functional changes.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Jan Kiszka 2010-06-13 14:15:35 +02:00 • committed by Blue Swirl
parent 6982d6647e
commit 27bb0b2d6f
2 changed files with 226 additions and 218 deletions
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413
hw/hpet.c
View file

@ -37,21 +37,47 @@
#define DPRINTF(...) #define DPRINTF(...)
#endif #endif
struct HPETState;
typedef struct HPETTimer { /* timers */
uint8_t tn; /*timer number*/
QEMUTimer *qemu_timer;
struct HPETState *state;
/* Memory-mapped, software visible timer registers */
uint64_t config; /* configuration/cap */
uint64_t cmp; /* comparator */
uint64_t fsb; /* FSB route, not supported now */
/* Hidden register state */
uint64_t period; /* Last value written to comparator */
uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit
* mode. Next pop will be actual timer expiration.
*/
} HPETTimer;
typedef struct HPETState {
uint64_t hpet_offset;
qemu_irq *irqs;
HPETTimer timer[HPET_NUM_TIMERS];
/* Memory-mapped, software visible registers */
uint64_t capability; /* capabilities */
uint64_t config; /* configuration */
uint64_t isr; /* interrupt status reg */
uint64_t hpet_counter; /* main counter */
} HPETState;
static HPETState *hpet_statep; static HPETState *hpet_statep;
uint32_t hpet_in_legacy_mode(void) uint32_t hpet_in_legacy_mode(void)
{ {
if (hpet_statep) if (!hpet_statep) {
return hpet_statep->config & HPET_CFG_LEGACY;
else
return 0; return 0;
}
return hpet_statep->config & HPET_CFG_LEGACY;
} }
static uint32_t timer_int_route(struct HPETTimer *timer) static uint32_t timer_int_route(struct HPETTimer *timer)
{ {
uint32_t route; return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
route = (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
return route;
} }
static uint32_t hpet_enabled(void) static uint32_t hpet_enabled(void)
@ -108,9 +134,7 @@ static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
static uint64_t hpet_get_ticks(void) static uint64_t hpet_get_ticks(void)
{ {
uint64_t ticks; return ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset);
ticks = ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset);
return ticks;
} }
/* /*
@ -121,12 +145,14 @@ static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
if (t->config & HPET_TN_32BIT) { if (t->config & HPET_TN_32BIT) {
uint32_t diff, cmp; uint32_t diff, cmp;
cmp = (uint32_t)t->cmp; cmp = (uint32_t)t->cmp;
diff = cmp - (uint32_t)current; diff = cmp - (uint32_t)current;
diff = (int32_t)diff > 0 ? diff : (uint32_t)0; diff = (int32_t)diff > 0 ? diff : (uint32_t)0;
return (uint64_t)diff; return (uint64_t)diff;
} else { } else {
uint64_t diff, cmp; uint64_t diff, cmp;
cmp = t->cmp; cmp = t->cmp;
diff = cmp - current; diff = cmp - current;
diff = (int64_t)diff > 0 ? diff : (uint64_t)0; diff = (int64_t)diff > 0 ? diff : (uint64_t)0;
@ -136,7 +162,6 @@ static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
static void update_irq(struct HPETTimer *timer) static void update_irq(struct HPETTimer *timer)
{ {
qemu_irq irq;
int route; int route;
if (timer->tn <= 1 && hpet_in_legacy_mode()) { if (timer->tn <= 1 && hpet_in_legacy_mode()) {
@ -144,22 +169,20 @@ static void update_irq(struct HPETTimer *timer)
* timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC, * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
* timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC. * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
*/ */
if (timer->tn == 0) { route = (timer->tn == 0) ? 0 : 8;
irq=timer->state->irqs[0];
} else
irq=timer->state->irqs[8];
} else { } else {
route=timer_int_route(timer); route = timer_int_route(timer);
irq=timer->state->irqs[route];
} }
if (timer_enabled(timer) && hpet_enabled()) { if (!timer_enabled(timer) || !hpet_enabled()) {
qemu_irq_pulse(irq); return;
} }
qemu_irq_pulse(timer->state->irqs[route]);
} }
static void hpet_pre_save(void *opaque) static void hpet_pre_save(void *opaque)
{ {
HPETState *s = opaque; HPETState *s = opaque;
/* save current counter value */ /* save current counter value */
s->hpet_counter = hpet_get_ticks(); s->hpet_counter = hpet_get_ticks();
} }
@ -212,7 +235,7 @@ static const VMStateDescription vmstate_hpet = {
*/ */
static void hpet_timer(void *opaque) static void hpet_timer(void *opaque)
{ {
HPETTimer *t = (HPETTimer*)opaque; HPETTimer *t = opaque;
uint64_t diff; uint64_t diff;
uint64_t period = t->period; uint64_t period = t->period;
@ -220,20 +243,22 @@ static void hpet_timer(void *opaque)
if (timer_is_periodic(t) && period != 0) { if (timer_is_periodic(t) && period != 0) {
if (t->config & HPET_TN_32BIT) { if (t->config & HPET_TN_32BIT) {
while (hpet_time_after(cur_tick, t->cmp)) while (hpet_time_after(cur_tick, t->cmp)) {
t->cmp = (uint32_t)(t->cmp + t->period); t->cmp = (uint32_t)(t->cmp + t->period);
} else }
while (hpet_time_after64(cur_tick, t->cmp)) } else {
while (hpet_time_after64(cur_tick, t->cmp)) {
t->cmp += period; t->cmp += period;
}
}
diff = hpet_calculate_diff(t, cur_tick); diff = hpet_calculate_diff(t, cur_tick);
qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) qemu_mod_timer(t->qemu_timer,
+ (int64_t)ticks_to_ns(diff)); qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff));
} else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
if (t->wrap_flag) { if (t->wrap_flag) {
diff = hpet_calculate_diff(t, cur_tick); diff = hpet_calculate_diff(t, cur_tick);
qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) +
+ (int64_t)ticks_to_ns(diff)); (int64_t)ticks_to_ns(diff));
t->wrap_flag = 0; t->wrap_flag = 0;
} }
} }
@ -260,8 +285,8 @@ static void hpet_set_timer(HPETTimer *t)
t->wrap_flag = 1; t->wrap_flag = 1;
} }
} }
qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) qemu_mod_timer(t->qemu_timer,
+ (int64_t)ticks_to_ns(diff)); qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff));
} }
static void hpet_del_timer(HPETTimer *t) static void hpet_del_timer(HPETTimer *t)
@ -285,7 +310,7 @@ static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr) static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
{ {
HPETState *s = (HPETState *)opaque; HPETState *s = opaque;
uint64_t cur_tick, index; uint64_t cur_tick, index;
DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr); DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
@ -293,57 +318,60 @@ static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
/*address range of all TN regs*/ /*address range of all TN regs*/
if (index >= 0x100 && index <= 0x3ff) { if (index >= 0x100 && index <= 0x3ff) {
uint8_t timer_id = (addr - 0x100) / 0x20; uint8_t timer_id = (addr - 0x100) / 0x20;
HPETTimer *timer = &s->timer[timer_id];
if (timer_id > HPET_NUM_TIMERS - 1) { if (timer_id > HPET_NUM_TIMERS - 1) {
DPRINTF("qemu: timer id out of range\n"); DPRINTF("qemu: timer id out of range\n");
return 0; return 0;
} }
HPETTimer *timer = &s->timer[timer_id];
switch ((addr - 0x100) % 0x20) { switch ((addr - 0x100) % 0x20) {
case HPET_TN_CFG: case HPET_TN_CFG:
return timer->config; return timer->config;
case HPET_TN_CFG + 4: // Interrupt capabilities case HPET_TN_CFG + 4: // Interrupt capabilities
return timer->config >> 32; return timer->config >> 32;
case HPET_TN_CMP: // comparator register case HPET_TN_CMP: // comparator register
return timer->cmp; return timer->cmp;
case HPET_TN_CMP + 4: case HPET_TN_CMP + 4:
return timer->cmp >> 32; return timer->cmp >> 32;
case HPET_TN_ROUTE: case HPET_TN_ROUTE:
return timer->fsb >> 32; return timer->fsb >> 32;
default: default:
DPRINTF("qemu: invalid hpet_ram_readl\n"); DPRINTF("qemu: invalid hpet_ram_readl\n");
break; break;
} }
} else { } else {
switch (index) { switch (index) {
case HPET_ID: case HPET_ID:
return s->capability; return s->capability;
case HPET_PERIOD: case HPET_PERIOD:
return s->capability >> 32; return s->capability >> 32;
case HPET_CFG: case HPET_CFG:
return s->config; return s->config;
case HPET_CFG + 4: case HPET_CFG + 4:
DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n"); DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
return 0; return 0;
case HPET_COUNTER: case HPET_COUNTER:
if (hpet_enabled()) if (hpet_enabled()) {
cur_tick = hpet_get_ticks(); cur_tick = hpet_get_ticks();
else } else {
cur_tick = s->hpet_counter; cur_tick = s->hpet_counter;
DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick); }
return cur_tick; DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick);
case HPET_COUNTER + 4: return cur_tick;
if (hpet_enabled()) case HPET_COUNTER + 4:
cur_tick = hpet_get_ticks(); if (hpet_enabled()) {
else cur_tick = hpet_get_ticks();
cur_tick = s->hpet_counter; } else {
DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick); cur_tick = s->hpet_counter;
return cur_tick >> 32; }
case HPET_STATUS: DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick);
return s->isr; return cur_tick >> 32;
default: case HPET_STATUS:
DPRINTF("qemu: invalid hpet_ram_readl\n"); return s->isr;
break; default:
DPRINTF("qemu: invalid hpet_ram_readl\n");
break;
} }
} }
return 0; return 0;
@ -369,7 +397,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
uint32_t value) uint32_t value)
{ {
int i; int i;
HPETState *s = (HPETState *)opaque; HPETState *s = opaque;
uint64_t old_val, new_val, val, index; uint64_t old_val, new_val, val, index;
DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value); DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
@ -380,133 +408,137 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
/*address range of all TN regs*/ /*address range of all TN regs*/
if (index >= 0x100 && index <= 0x3ff) { if (index >= 0x100 && index <= 0x3ff) {
uint8_t timer_id = (addr - 0x100) / 0x20; uint8_t timer_id = (addr - 0x100) / 0x20;
DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
HPETTimer *timer = &s->timer[timer_id]; HPETTimer *timer = &s->timer[timer_id];
DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
if (timer_id > HPET_NUM_TIMERS - 1) { if (timer_id > HPET_NUM_TIMERS - 1) {
DPRINTF("qemu: timer id out of range\n"); DPRINTF("qemu: timer id out of range\n");
return; return;
} }
switch ((addr - 0x100) % 0x20) { switch ((addr - 0x100) % 0x20) {
case HPET_TN_CFG: case HPET_TN_CFG:
DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n"); DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
timer->config = (timer->config & 0xffffffff00000000ULL) | val; timer->config = (timer->config & 0xffffffff00000000ULL) | val;
if (new_val & HPET_TN_32BIT) { if (new_val & HPET_TN_32BIT) {
timer->cmp = (uint32_t)timer->cmp; timer->cmp = (uint32_t)timer->cmp;
timer->period = (uint32_t)timer->period; timer->period = (uint32_t)timer->period;
} }
if (new_val & HPET_TIMER_TYPE_LEVEL) { if (new_val & HPET_TN_TYPE_LEVEL) {
printf("qemu: level-triggered hpet not supported\n"); printf("qemu: level-triggered hpet not supported\n");
exit (-1); exit (-1);
} }
break;
break; case HPET_TN_CFG + 4: // Interrupt capabilities
case HPET_TN_CFG + 4: // Interrupt capabilities DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n"); break;
break; case HPET_TN_CMP: // comparator register
case HPET_TN_CMP: // comparator register DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n"); if (timer->config & HPET_TN_32BIT) {
if (timer->config & HPET_TN_32BIT) new_val = (uint32_t)new_val;
new_val = (uint32_t)new_val; }
if (!timer_is_periodic(timer) || if (!timer_is_periodic(timer)
(timer->config & HPET_TN_SETVAL)) || (timer->config & HPET_TN_SETVAL)) {
timer->cmp = (timer->cmp & 0xffffffff00000000ULL) timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
| new_val; }
if (timer_is_periodic(timer)) { if (timer_is_periodic(timer)) {
/* /*
* FIXME: Clamp period to reasonable min value? * FIXME: Clamp period to reasonable min value?
* Clamp period to reasonable max value * Clamp period to reasonable max value
*/ */
new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
timer->period = (timer->period & 0xffffffff00000000ULL) timer->period =
| new_val; (timer->period & 0xffffffff00000000ULL) | new_val;
}
timer->config &= ~HPET_TN_SETVAL;
if (hpet_enabled()) {
hpet_set_timer(timer);
}
break;
case HPET_TN_CMP + 4: // comparator register high order
DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
if (!timer_is_periodic(timer)
|| (timer->config & HPET_TN_SETVAL)) {
timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
} else {
/*
* FIXME: Clamp period to reasonable min value?
* Clamp period to reasonable max value
*/
new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
timer->period =
(timer->period & 0xffffffffULL) | new_val << 32;
} }
timer->config &= ~HPET_TN_SETVAL; timer->config &= ~HPET_TN_SETVAL;
if (hpet_enabled()) if (hpet_enabled()) {
hpet_set_timer(timer); hpet_set_timer(timer);
break;
case HPET_TN_CMP + 4: // comparator register high order
DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
if (!timer_is_periodic(timer) ||
(timer->config & HPET_TN_SETVAL))
timer->cmp = (timer->cmp & 0xffffffffULL)
| new_val << 32;
else {
/*
* FIXME: Clamp period to reasonable min value?
* Clamp period to reasonable max value
*/
new_val &= (timer->config
& HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
timer->period = (timer->period & 0xffffffffULL)
| new_val << 32;
} }
timer->config &= ~HPET_TN_SETVAL;
if (hpet_enabled())
hpet_set_timer(timer);
break;
case HPET_TN_ROUTE + 4:
DPRINTF("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
break;
default:
DPRINTF("qemu: invalid hpet_ram_writel\n");
break; break;
case HPET_TN_ROUTE + 4:
DPRINTF("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
break;
default:
DPRINTF("qemu: invalid hpet_ram_writel\n");
break;
} }
return; return;
} else { } else {
switch (index) { switch (index) {
case HPET_ID: case HPET_ID:
return; return;
case HPET_CFG: case HPET_CFG:
val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
s->config = (s->config & 0xffffffff00000000ULL) | val; s->config = (s->config & 0xffffffff00000000ULL) | val;
if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) { if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
/* Enable main counter and interrupt generation. */ /* Enable main counter and interrupt generation. */
s->hpet_offset = ticks_to_ns(s->hpet_counter) s->hpet_offset =
- qemu_get_clock(vm_clock); ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
for (i = 0; i < HPET_NUM_TIMERS; i++) for (i = 0; i < HPET_NUM_TIMERS; i++) {
if ((&s->timer[i])->cmp != ~0ULL) if ((&s->timer[i])->cmp != ~0ULL) {
hpet_set_timer(&s->timer[i]); hpet_set_timer(&s->timer[i]);
}
} }
else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) { } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
/* Halt main counter and disable interrupt generation. */ /* Halt main counter and disable interrupt generation. */
s->hpet_counter = hpet_get_ticks(); s->hpet_counter = hpet_get_ticks();
for (i = 0; i < HPET_NUM_TIMERS; i++) for (i = 0; i < HPET_NUM_TIMERS; i++) {
hpet_del_timer(&s->timer[i]); hpet_del_timer(&s->timer[i]);
} }
/* i8254 and RTC are disabled when HPET is in legacy mode */ }
if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) { /* i8254 and RTC are disabled when HPET is in legacy mode */
hpet_pit_disable(); if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
} else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) { hpet_pit_disable();
hpet_pit_enable(); } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
} hpet_pit_enable();
break; }
case HPET_CFG + 4: break;
DPRINTF("qemu: invalid HPET_CFG+4 write \n"); case HPET_CFG + 4:
break; DPRINTF("qemu: invalid HPET_CFG+4 write \n");
case HPET_STATUS: break;
/* FIXME: need to handle level-triggered interrupts */ case HPET_STATUS:
break; /* FIXME: need to handle level-triggered interrupts */
case HPET_COUNTER: break;
if (hpet_enabled()) case HPET_COUNTER:
printf("qemu: Writing counter while HPET enabled!\n"); if (hpet_enabled()) {
s->hpet_counter = (s->hpet_counter & 0xffffffff00000000ULL) printf("qemu: Writing counter while HPET enabled!\n");
| value; }
DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n", s->hpet_counter =
value, s->hpet_counter); (s->hpet_counter & 0xffffffff00000000ULL) | value;
break; DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
case HPET_COUNTER + 4: value, s->hpet_counter);
if (hpet_enabled()) break;
printf("qemu: Writing counter while HPET enabled!\n"); case HPET_COUNTER + 4:
s->hpet_counter = (s->hpet_counter & 0xffffffffULL) if (hpet_enabled()) {
| (((uint64_t)value) << 32); printf("qemu: Writing counter while HPET enabled!\n");
DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n", }
value, s->hpet_counter); s->hpet_counter =
break; (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
default: DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
DPRINTF("qemu: invalid hpet_ram_writel\n"); value, s->hpet_counter);
break; break;
default:
DPRINTF("qemu: invalid hpet_ram_writel\n");
break;
} }
} }
} }
@ -533,13 +565,15 @@ static CPUWriteMemoryFunc * const hpet_ram_write[] = {
hpet_ram_writel, hpet_ram_writel,
}; };
static void hpet_reset(void *opaque) { static void hpet_reset(void *opaque)
{
HPETState *s = opaque; HPETState *s = opaque;
int i; int i;
static int count = 0; static int count = 0;
for (i=0; i<HPET_NUM_TIMERS; i++) { for (i = 0; i < HPET_NUM_TIMERS; i++) {
HPETTimer *timer = &s->timer[i]; HPETTimer *timer = &s->timer[i];
hpet_del_timer(timer); hpet_del_timer(timer);
timer->tn = i; timer->tn = i;
timer->cmp = ~0ULL; timer->cmp = ~0ULL;
@ -557,19 +591,22 @@ static void hpet_reset(void *opaque) {
s->capability = 0x8086a201ULL; s->capability = 0x8086a201ULL;
s->capability |= ((HPET_CLK_PERIOD) << 32); s->capability |= ((HPET_CLK_PERIOD) << 32);
s->config = 0ULL; s->config = 0ULL;
if (count > 0) if (count > 0) {
/* we don't enable pit when hpet_reset is first called (by hpet_init) /* we don't enable pit when hpet_reset is first called (by hpet_init)
* because hpet is taking over for pit here. On subsequent invocations, * because hpet is taking over for pit here. On subsequent invocations,
* hpet_reset is called due to system reset. At this point control must * hpet_reset is called due to system reset. At this point control must
* be returned to pit until SW reenables hpet. * be returned to pit until SW reenables hpet.
*/ */
hpet_pit_enable(); hpet_pit_enable();
}
count = 1; count = 1;
} }
void hpet_init(qemu_irq *irq) { void hpet_init(qemu_irq *irq)
{
int i, iomemtype; int i, iomemtype;
HPETTimer *timer;
HPETState *s; HPETState *s;
DPRINTF ("hpet_init\n"); DPRINTF ("hpet_init\n");
@ -577,8 +614,8 @@ void hpet_init(qemu_irq *irq) {
s = qemu_mallocz(sizeof(HPETState)); s = qemu_mallocz(sizeof(HPETState));
hpet_statep = s; hpet_statep = s;
s->irqs = irq; s->irqs = irq;
for (i=0; i<HPET_NUM_TIMERS; i++) { for (i = 0; i < HPET_NUM_TIMERS; i++) {
HPETTimer *timer = &s->timer[i]; timer = &s->timer[i];
timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer); timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer);
} }
vmstate_register(-1, &vmstate_hpet, s); vmstate_register(-1, &vmstate_hpet, s);

31
hw/hpet_emul.h
View file

@ -18,7 +18,6 @@
#define FS_PER_NS 1000000 #define FS_PER_NS 1000000
#define HPET_NUM_TIMERS 3 #define HPET_NUM_TIMERS 3
#define HPET_TIMER_TYPE_LEVEL 0x002
#define HPET_CFG_ENABLE 0x001 #define HPET_CFG_ENABLE 0x001
#define HPET_CFG_LEGACY 0x002 #define HPET_CFG_LEGACY 0x002
@ -33,7 +32,7 @@
#define HPET_TN_ROUTE 0x010 #define HPET_TN_ROUTE 0x010
#define HPET_CFG_WRITE_MASK 0x3 #define HPET_CFG_WRITE_MASK 0x3
#define HPET_TN_TYPE_LEVEL 0x002
#define HPET_TN_ENABLE 0x004 #define HPET_TN_ENABLE 0x004
#define HPET_TN_PERIODIC 0x008 #define HPET_TN_PERIODIC 0x008
#define HPET_TN_PERIODIC_CAP 0x010 #define HPET_TN_PERIODIC_CAP 0x010
@ -46,34 +45,6 @@
#define HPET_TN_INT_ROUTE_CAP_SHIFT 32 #define HPET_TN_INT_ROUTE_CAP_SHIFT 32
#define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U #define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U
struct HPETState;
typedef struct HPETTimer { /* timers */
uint8_t tn; /*timer number*/
QEMUTimer *qemu_timer;
struct HPETState *state;
/* Memory-mapped, software visible timer registers */
uint64_t config; /* configuration/cap */
uint64_t cmp; /* comparator */
uint64_t fsb; /* FSB route, not supported now */
/* Hidden register state */
uint64_t period; /* Last value written to comparator */
uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit
* mode. Next pop will be actual timer expiration.
*/
} HPETTimer;
typedef struct HPETState {
uint64_t hpet_offset;
qemu_irq *irqs;
HPETTimer timer[HPET_NUM_TIMERS];
/* Memory-mapped, software visible registers */
uint64_t capability; /* capabilities */
uint64_t config; /* configuration */
uint64_t isr; /* interrupt status reg */
uint64_t hpet_counter; /* main counter */
} HPETState;
#if defined TARGET_I386 #if defined TARGET_I386
extern uint32_t hpet_in_legacy_mode(void); extern uint32_t hpet_in_legacy_mode(void);
extern void hpet_init(qemu_irq *irq); extern void hpet_init(qemu_irq *irq);