mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-05 00:33:55 -06:00
target/riscv: Add kvm_riscv_get/put_regs_timer
Add kvm_riscv_get/put_regs_timer to synchronize virtual time context from KVM. To set register of RISCV_TIMER_REG(state) will occur a error from KVM on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter that adaping in QEMU. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220112081329.1835-11-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
parent
10f1ca27e0
commit
27abe66f31
2 changed files with 79 additions and 0 deletions
|
@ -273,6 +273,13 @@ struct CPURISCVState {
|
||||||
|
|
||||||
hwaddr kernel_addr;
|
hwaddr kernel_addr;
|
||||||
hwaddr fdt_addr;
|
hwaddr fdt_addr;
|
||||||
|
|
||||||
|
/* kvm timer */
|
||||||
|
bool kvm_timer_dirty;
|
||||||
|
uint64_t kvm_timer_time;
|
||||||
|
uint64_t kvm_timer_compare;
|
||||||
|
uint64_t kvm_timer_state;
|
||||||
|
uint64_t kvm_timer_frequency;
|
||||||
};
|
};
|
||||||
|
|
||||||
OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
|
OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
|
||||||
|
|
|
@ -40,6 +40,7 @@
|
||||||
#include "kvm_riscv.h"
|
#include "kvm_riscv.h"
|
||||||
#include "sbi_ecall_interface.h"
|
#include "sbi_ecall_interface.h"
|
||||||
#include "chardev/char-fe.h"
|
#include "chardev/char-fe.h"
|
||||||
|
#include "migration/migration.h"
|
||||||
|
|
||||||
static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
|
static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
|
||||||
uint64_t idx)
|
uint64_t idx)
|
||||||
|
@ -65,6 +66,9 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
|
||||||
#define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
|
#define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
|
||||||
KVM_REG_RISCV_CSR_REG(name))
|
KVM_REG_RISCV_CSR_REG(name))
|
||||||
|
|
||||||
|
#define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \
|
||||||
|
KVM_REG_RISCV_TIMER_REG(name))
|
||||||
|
|
||||||
#define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx)
|
#define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx)
|
||||||
|
|
||||||
#define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
|
#define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
|
||||||
|
@ -85,6 +89,22 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
|
||||||
} \
|
} \
|
||||||
} while (0)
|
} while (0)
|
||||||
|
|
||||||
|
#define KVM_RISCV_GET_TIMER(cs, env, name, reg) \
|
||||||
|
do { \
|
||||||
|
int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \
|
||||||
|
if (ret) { \
|
||||||
|
abort(); \
|
||||||
|
} \
|
||||||
|
} while (0)
|
||||||
|
|
||||||
|
#define KVM_RISCV_SET_TIMER(cs, env, name, reg) \
|
||||||
|
do { \
|
||||||
|
int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, time), ®); \
|
||||||
|
if (ret) { \
|
||||||
|
abort(); \
|
||||||
|
} \
|
||||||
|
} while (0)
|
||||||
|
|
||||||
static int kvm_riscv_get_regs_core(CPUState *cs)
|
static int kvm_riscv_get_regs_core(CPUState *cs)
|
||||||
{
|
{
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
|
@ -236,6 +256,58 @@ static int kvm_riscv_put_regs_fp(CPUState *cs)
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void kvm_riscv_get_regs_timer(CPUState *cs)
|
||||||
|
{
|
||||||
|
CPURISCVState *env = &RISCV_CPU(cs)->env;
|
||||||
|
|
||||||
|
if (env->kvm_timer_dirty) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time);
|
||||||
|
KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare);
|
||||||
|
KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state);
|
||||||
|
KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency);
|
||||||
|
|
||||||
|
env->kvm_timer_dirty = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void kvm_riscv_put_regs_timer(CPUState *cs)
|
||||||
|
{
|
||||||
|
uint64_t reg;
|
||||||
|
CPURISCVState *env = &RISCV_CPU(cs)->env;
|
||||||
|
|
||||||
|
if (!env->kvm_timer_dirty) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time);
|
||||||
|
KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* To set register of RISCV_TIMER_REG(state) will occur a error from KVM
|
||||||
|
* on env->kvm_timer_state == 0, It's better to adapt in KVM, but it
|
||||||
|
* doesn't matter that adaping in QEMU now.
|
||||||
|
* TODO If KVM changes, adapt here.
|
||||||
|
*/
|
||||||
|
if (env->kvm_timer_state) {
|
||||||
|
KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* For now, migration will not work between Hosts with different timer
|
||||||
|
* frequency. Therefore, we should check whether they are the same here
|
||||||
|
* during the migration.
|
||||||
|
*/
|
||||||
|
if (migration_is_running(migrate_get_current()->state)) {
|
||||||
|
KVM_RISCV_GET_TIMER(cs, env, frequency, reg);
|
||||||
|
if (reg != env->kvm_timer_frequency) {
|
||||||
|
error_report("Dst Hosts timer frequency != Src Hosts");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
env->kvm_timer_dirty = false;
|
||||||
|
}
|
||||||
|
|
||||||
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
|
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
|
||||||
KVM_CAP_LAST_INFO
|
KVM_CAP_LAST_INFO
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue