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target/riscv: Use aesenc_SB_SR_MC_AK

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This implements the AES64ESM instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-06-02 14:14:04 -07:00
parent 607a5f9d62
commit 274f33765a
1 changed files with 6 additions and 1 deletions
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7
target/riscv/crypto_helper.c
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@ -198,7 +198,12 @@ static inline target_ulong aes64_operation(target_ulong rs1, target_ulong rs2,
target_ulong HELPER(aes64esm)(target_ulong rs1, target_ulong rs2) target_ulong HELPER(aes64esm)(target_ulong rs1, target_ulong rs2)
{ {
return aes64_operation(rs1, rs2, true, true); AESState t;
t.d[HOST_BIG_ENDIAN] = rs1;
t.d[!HOST_BIG_ENDIAN] = rs2;
aesenc_SB_SR_MC_AK(&t, &t, &aes_zero, false);
return t.d[HOST_BIG_ENDIAN];
} }
target_ulong HELPER(aes64es)(target_ulong rs1, target_ulong rs2) target_ulong HELPER(aes64es)(target_ulong rs1, target_ulong rs2)