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cpu: Move exception_index field from CPU_COMMON to CPUState

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Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber 2013-08-26 08:31:06 +02:00
parent 6f03bef0ff
commit 27103424c4
60 changed files with 389 additions and 319 deletions
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2
target-openrisc/cpu.c
View file

@ -48,7 +48,7 @@ static void openrisc_cpu_reset(CPUState *s)
cpu->env.pc = 0x100;
cpu->env.sr = SR_FO | SR_SM;
cpu->env.exception_index = -1;
s->exception_index = -1;
cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;

4
target-openrisc/exception.c
View file

@ -22,6 +22,8 @@
void QEMU_NORETURN raise_exception(OpenRISCCPU *cpu, uint32_t excp)
{
cpu->env.exception_index = excp;
CPUState *cs = CPU(cpu);
cs->exception_index = excp;
cpu_loop_exit(&cpu->env);
}

12
target-openrisc/interrupt.c
View file

@ -27,9 +27,9 @@
void openrisc_cpu_do_interrupt(CPUState *cs)
{
#ifndef CONFIG_USER_ONLY
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
CPUOpenRISCState *env = &cpu->env;
#ifndef CONFIG_USER_ONLY
env->epcr = env->pc;
if (env->flags & D_FLAG) {
@ -37,7 +37,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->sr |= SR_DSX;
env->epcr -= 4;
}
if (env->exception_index == EXCP_SYSCALL) {
if (cs->exception_index == EXCP_SYSCALL) {
env->epcr += 4;
}
@ -54,12 +54,12 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
if (env->exception_index > 0 && env->exception_index < EXCP_NR) {
env->pc = (env->exception_index << 8);
if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) {
env->pc = (cs->exception_index << 8);
} else {
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
}
#endif
env->exception_index = -1;
cs->exception_index = -1;
}

3
target-openrisc/mmu.c
View file

@ -139,6 +139,7 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu,
target_ulong address,
int rw, int tlb_error)
{
CPUState *cs = CPU(cpu);
int exception = 0;
switch (tlb_error) {
@ -169,7 +170,7 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu,
#endif
}
cpu->env.exception_index = exception;
cs->exception_index = exception;
cpu->env.eear = address;
}