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cpu: Move exception_index field from CPU_COMMON to CPUState

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Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber 2013-08-26 08:31:06 +02:00
parent 6f03bef0ff
commit 27103424c4
60 changed files with 389 additions and 319 deletions
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31
target-mips/helper.c
View file

@ -204,6 +204,7 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
int rw, int tlb_error)
{
CPUState *cs = CPU(mips_env_get_cpu(env));
int exception = 0, error_code = 0;
switch (tlb_error) {
@ -249,7 +250,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
#endif
env->exception_index = exception;
cs->exception_index = exception;
env->error_code = error_code;
}
@ -404,27 +405,29 @@ static void set_hflags_for_handler (CPUMIPSState *env)
void mips_cpu_do_interrupt(CPUState *cs)
{
#if !defined(CONFIG_USER_ONLY)
MIPSCPU *cpu = MIPS_CPU(cs);
CPUMIPSState *env = &cpu->env;
#if !defined(CONFIG_USER_ONLY)
target_ulong offset;
int cause = -1;
const char *name;
if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
name = "unknown";
else
name = excp_names[env->exception_index];
} else {
name = excp_names[cs->exception_index];
}
qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
__func__, env->active_tc.PC, env->CP0_EPC, name);
}
if (env->exception_index == EXCP_EXT_INTERRUPT &&
(env->hflags & MIPS_HFLAG_DM))
env->exception_index = EXCP_DINT;
if (cs->exception_index == EXCP_EXT_INTERRUPT &&
(env->hflags & MIPS_HFLAG_DM)) {
cs->exception_index = EXCP_DINT;
}
offset = 0x180;
switch (env->exception_index) {
switch (cs->exception_index) {
case EXCP_DSS:
env->CP0_Debug |= 1 << CP0DB_DSS;
/* Debug single step cannot be raised inside a delay slot and
@ -632,11 +635,11 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
break;
default:
qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index);
printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
qemu_log("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
printf("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
exit(1);
}
if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
__func__, env->active_tc.PC, env->CP0_EPC, cause,
@ -644,7 +647,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->CP0_DEPC);
}
#endif
env->exception_index = EXCP_NONE;
cs->exception_index = EXCP_NONE;
}
#if !defined(CONFIG_USER_ONLY)

9
target-mips/op_helper.c
View file

@ -38,10 +38,12 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
int error_code,
uintptr_t pc)
{
CPUState *cs = CPU(mips_env_get_cpu(env));
if (exception < EXCP_SC) {
qemu_log("%s: %d %d\n", __func__, exception, error_code);
}
env->exception_index = exception;
cs->exception_index = exception;
env->error_code = error_code;
if (pc) {
@ -2147,11 +2149,12 @@ void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
MIPSCPU *cpu = mips_env_get_cpu(env);
CPUState *cs = CPU(cpu);
int ret;
ret = mips_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (ret) {
do_raise_exception_err(env, env->exception_index,
do_raise_exception_err(env, cs->exception_index,
env->error_code, retaddr);
}
}

4
target-mips/translate.c
View file

@ -15929,10 +15929,8 @@ MIPSCPU *cpu_mips_init(const char *cpu_model)
void cpu_state_reset(CPUMIPSState *env)
{
#ifndef CONFIG_USER_ONLY
MIPSCPU *cpu = mips_env_get_cpu(env);
CPUState *cs = CPU(cpu);
#endif
/* Reset registers to their default values */
env->CP0_PRid = env->cpu_model->CP0_PRid;
@ -16063,7 +16061,7 @@ void cpu_state_reset(CPUMIPSState *env)
}
#endif
compute_hflags(env);
env->exception_index = EXCP_NONE;
cs->exception_index = EXCP_NONE;
}
void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, int pc_pos)