mirror of
https://github.com/Motorhead1991/qemu.git
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target-ppc: convert logical instructions to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5506 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32
parent
e1571908a2
commit
26d6736245
4 changed files with 248 additions and 394 deletions
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@ -1277,63 +1277,56 @@ GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
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#endif
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/*** Integer logical ***/
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#define __GEN_LOGICAL2(name, opc2, opc3, type) \
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GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
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#define GEN_LOGICAL2(name, tcg_op, opc, type) \
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GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
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{ \
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tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \
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tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
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gen_op_##name(); \
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
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tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
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cpu_gpr[rB(ctx->opcode)]); \
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if (unlikely(Rc(ctx->opcode) != 0)) \
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gen_set_Rc0(ctx, cpu_T[0]); \
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gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
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}
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#define GEN_LOGICAL2(name, opc, type) \
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__GEN_LOGICAL2(name, 0x1C, opc, type)
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#define GEN_LOGICAL1(name, opc, type) \
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#define GEN_LOGICAL1(name, tcg_op, opc, type) \
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GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
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{ \
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tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \
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gen_op_##name(); \
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
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tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
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if (unlikely(Rc(ctx->opcode) != 0)) \
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gen_set_Rc0(ctx, cpu_T[0]); \
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gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
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}
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/* and & and. */
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GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
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GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
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/* andc & andc. */
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GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
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GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
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/* andi. */
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GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
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{
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tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
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tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode));
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
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gen_set_Rc0(ctx, cpu_T[0]);
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tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
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gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
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}
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/* andis. */
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GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
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{
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tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
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tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode) << 16);
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
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gen_set_Rc0(ctx, cpu_T[0]);
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tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
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gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
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}
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/* cntlzw */
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GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
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GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
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{
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tcg_gen_helper_1_1(helper_cntlzw, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
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if (unlikely(Rc(ctx->opcode) != 0))
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gen_set_Rc0(ctx, cpu_gpr[rS(ctx->opcode)]);
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}
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/* eqv & eqv. */
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GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
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GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
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/* extsb & extsb. */
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GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
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GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
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/* extsh & extsh. */
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GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
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GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
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/* nand & nand. */
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GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
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GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
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/* nor & nor. */
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GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
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GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
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/* or & or. */
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GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
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{
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@ -1344,55 +1337,54 @@ GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
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rb = rB(ctx->opcode);
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/* Optimisation for mr. ri case */
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if (rs != ra || rs != rb) {
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tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
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if (rs != rb) {
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tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
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gen_op_or();
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}
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tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
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if (rs != rb)
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tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
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else
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tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
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if (unlikely(Rc(ctx->opcode) != 0))
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gen_set_Rc0(ctx, cpu_T[0]);
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gen_set_Rc0(ctx, cpu_gpr[ra]);
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} else if (unlikely(Rc(ctx->opcode) != 0)) {
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tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
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gen_set_Rc0(ctx, cpu_T[0]);
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gen_set_Rc0(ctx, cpu_gpr[rs]);
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#if defined(TARGET_PPC64)
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} else {
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int prio = 0;
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switch (rs) {
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case 1:
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/* Set process priority to low */
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gen_op_store_pri(2);
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prio = 2;
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break;
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case 6:
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/* Set process priority to medium-low */
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gen_op_store_pri(3);
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prio = 3;
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break;
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case 2:
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/* Set process priority to normal */
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gen_op_store_pri(4);
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prio = 4;
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break;
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#if !defined(CONFIG_USER_ONLY)
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case 31:
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if (ctx->supervisor > 0) {
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/* Set process priority to very low */
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gen_op_store_pri(1);
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prio = 1;
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}
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break;
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case 5:
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if (ctx->supervisor > 0) {
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/* Set process priority to medium-hight */
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gen_op_store_pri(5);
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prio = 5;
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}
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break;
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case 3:
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if (ctx->supervisor > 0) {
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/* Set process priority to high */
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gen_op_store_pri(6);
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prio = 6;
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}
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break;
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case 7:
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if (ctx->supervisor > 1) {
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/* Set process priority to very high */
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gen_op_store_pri(7);
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prio = 7;
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}
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break;
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#endif
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@ -1400,26 +1392,29 @@ GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
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/* nop */
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break;
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}
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if (prio) {
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TCGv temp = tcg_temp_new(TCG_TYPE_TL);
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tcg_gen_ld_tl(temp, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
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tcg_gen_andi_tl(temp, temp, ~0x001C000000000000ULL);
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tcg_gen_ori_tl(temp, temp, ((uint64_t)prio) << 50);
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tcg_gen_st_tl(temp, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
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tcg_temp_free(temp);
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}
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#endif
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}
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}
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/* orc & orc. */
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GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
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GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
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/* xor & xor. */
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GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
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{
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tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
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/* Optimisation for "set to zero" case */
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if (rS(ctx->opcode) != rB(ctx->opcode)) {
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tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
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gen_op_xor();
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} else {
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tcg_gen_movi_tl(cpu_T[0], 0);
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}
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
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if (rS(ctx->opcode) != rB(ctx->opcode))
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tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
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else
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tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
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if (unlikely(Rc(ctx->opcode) != 0))
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gen_set_Rc0(ctx, cpu_T[0]);
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gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
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}
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/* ori */
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GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
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@ -1431,10 +1426,7 @@ GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
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/* XXX: should handle special NOPs for POWER series */
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return;
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}
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tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
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if (likely(uimm != 0))
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gen_op_ori(uimm);
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
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tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
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}
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/* oris */
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GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
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@ -1445,10 +1437,7 @@ GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
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/* NOP */
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return;
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}
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tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
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if (likely(uimm != 0))
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gen_op_ori(uimm << 16);
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
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tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
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}
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/* xori */
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GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
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@ -1459,12 +1448,8 @@ GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
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/* NOP */
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return;
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}
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tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
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if (likely(uimm != 0))
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gen_op_xori(uimm);
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
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tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
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}
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/* xoris */
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GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
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{
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@ -1474,30 +1459,29 @@ GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
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/* NOP */
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return;
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}
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tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
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if (likely(uimm != 0))
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gen_op_xori(uimm << 16);
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
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tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
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}
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/* popcntb : PowerPC 2.03 specification */
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GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
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{
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tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
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#if defined(TARGET_PPC64)
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if (ctx->sf_mode)
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gen_op_popcntb_64();
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tcg_gen_helper_1_1(helper_popcntb_64, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
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else
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#endif
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gen_op_popcntb();
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
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tcg_gen_helper_1_1(helper_popcntb, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
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}
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#if defined(TARGET_PPC64)
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/* extsw & extsw. */
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GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
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GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
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/* cntlzd */
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GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
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GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
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{
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tcg_gen_helper_1_1(helper_cntlzd, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
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if (unlikely(Rc(ctx->opcode) != 0))
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gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
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}
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#endif
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/*** Integer rotate ***/
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@ -1759,54 +1743,141 @@ GEN_PPC64_R4(rldimi, 0x1E, 0x06);
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/*** Integer shift ***/
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/* slw & slw. */
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__GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
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GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
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{
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TCGv temp;
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int l1, l2;
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l1 = gen_new_label();
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l2 = gen_new_label();
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temp = tcg_temp_local_new(TCG_TYPE_TL);
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tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x20);
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tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
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tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
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tcg_gen_br(l2);
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gen_set_label(l1);
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tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x3f);
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tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
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tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
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gen_set_label(l2);
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tcg_temp_free(temp);
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if (unlikely(Rc(ctx->opcode) != 0))
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gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
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}
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/* sraw & sraw. */
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__GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
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GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
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{
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tcg_gen_helper_1_2(helper_sraw, cpu_gpr[rA(ctx->opcode)],
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cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
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if (unlikely(Rc(ctx->opcode) != 0))
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gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
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}
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/* srawi & srawi. */
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GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
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{
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int mb, me;
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tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
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if (SH(ctx->opcode) != 0) {
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tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
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mb = 32 - SH(ctx->opcode);
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me = 31;
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#if defined(TARGET_PPC64)
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mb += 32;
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me += 32;
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#endif
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gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
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int sh = SH(ctx->opcode);
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if (sh != 0) {
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int l1, l2;
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TCGv temp;
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l1 = gen_new_label();
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l2 = gen_new_label();
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temp = tcg_temp_local_new(TCG_TYPE_TL);
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tcg_gen_ext32s_tl(temp, cpu_gpr[rS(ctx->opcode)]);
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tcg_gen_brcondi_tl(TCG_COND_GE, temp, 0, l1);
|
||||
tcg_gen_andi_tl(temp, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
|
||||
tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
|
||||
tcg_gen_ori_i32(cpu_xer, cpu_xer, 1 << XER_CA);
|
||||
tcg_gen_br(l2);
|
||||
gen_set_label(l1);
|
||||
tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
||||
gen_set_label(l2);
|
||||
tcg_gen_ext32s_tl(temp, cpu_gpr[rS(ctx->opcode)]);
|
||||
tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], temp, sh);
|
||||
tcg_temp_free(temp);
|
||||
} else {
|
||||
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
|
||||
tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
||||
}
|
||||
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
||||
if (unlikely(Rc(ctx->opcode) != 0))
|
||||
gen_set_Rc0(ctx, cpu_T[0]);
|
||||
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
|
||||
}
|
||||
/* srw & srw. */
|
||||
__GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
|
||||
GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
|
||||
{
|
||||
TCGv temp;
|
||||
int l1, l2;
|
||||
l1 = gen_new_label();
|
||||
l2 = gen_new_label();
|
||||
|
||||
temp = tcg_temp_local_new(TCG_TYPE_TL);
|
||||
tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x20);
|
||||
tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
|
||||
tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
||||
tcg_gen_br(l2);
|
||||
gen_set_label(l1);
|
||||
tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x3f);
|
||||
tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
|
||||
tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
|
||||
gen_set_label(l2);
|
||||
tcg_temp_free(temp);
|
||||
if (unlikely(Rc(ctx->opcode) != 0))
|
||||
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
|
||||
}
|
||||
#if defined(TARGET_PPC64)
|
||||
/* sld & sld. */
|
||||
__GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
|
||||
GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
|
||||
{
|
||||
TCGv temp;
|
||||
int l1, l2;
|
||||
l1 = gen_new_label();
|
||||
l2 = gen_new_label();
|
||||
|
||||
temp = tcg_temp_local_new(TCG_TYPE_TL);
|
||||
tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x40);
|
||||
tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
|
||||
tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
||||
tcg_gen_br(l2);
|
||||
gen_set_label(l1);
|
||||
tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x7f);
|
||||
tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
|
||||
gen_set_label(l2);
|
||||
tcg_temp_free(temp);
|
||||
if (unlikely(Rc(ctx->opcode) != 0))
|
||||
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
|
||||
}
|
||||
/* srad & srad. */
|
||||
__GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
|
||||
GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
|
||||
{
|
||||
tcg_gen_helper_1_2(helper_srad, cpu_gpr[rA(ctx->opcode)],
|
||||
cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
|
||||
if (unlikely(Rc(ctx->opcode) != 0))
|
||||
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
|
||||
}
|
||||
/* sradi & sradi. */
|
||||
static always_inline void gen_sradi (DisasContext *ctx, int n)
|
||||
{
|
||||
uint64_t mask;
|
||||
int sh, mb, me;
|
||||
|
||||
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
||||
sh = SH(ctx->opcode) + (n << 5);
|
||||
int sh = SH(ctx->opcode) + (n << 5);
|
||||
if (sh != 0) {
|
||||
tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
|
||||
mb = 64 - SH(ctx->opcode);
|
||||
me = 63;
|
||||
mask = MASK(mb, me);
|
||||
gen_op_sradi(sh, mask >> 32, mask);
|
||||
int l1, l2;
|
||||
TCGv temp;
|
||||
l1 = gen_new_label();
|
||||
l2 = gen_new_label();
|
||||
tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
|
||||
temp = tcg_temp_new(TCG_TYPE_TL);
|
||||
tcg_gen_andi_tl(temp, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
|
||||
tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
|
||||
tcg_gen_ori_i32(cpu_xer, cpu_xer, 1 << XER_CA);
|
||||
tcg_gen_br(l2);
|
||||
gen_set_label(l1);
|
||||
tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
||||
gen_set_label(l2);
|
||||
tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
|
||||
} else {
|
||||
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
|
||||
tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
||||
}
|
||||
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
||||
if (unlikely(Rc(ctx->opcode) != 0))
|
||||
gen_set_Rc0(ctx, cpu_T[0]);
|
||||
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
|
||||
}
|
||||
GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
|
||||
{
|
||||
|
|
@ -1817,7 +1888,26 @@ GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
|
|||
gen_sradi(ctx, 1);
|
||||
}
|
||||
/* srd & srd. */
|
||||
__GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
|
||||
GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
|
||||
{
|
||||
TCGv temp;
|
||||
int l1, l2;
|
||||
l1 = gen_new_label();
|
||||
l2 = gen_new_label();
|
||||
|
||||
temp = tcg_temp_local_new(TCG_TYPE_TL);
|
||||
tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x40);
|
||||
tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
|
||||
tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
||||
tcg_gen_br(l2);
|
||||
gen_set_label(l1);
|
||||
tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x7f);
|
||||
tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
|
||||
gen_set_label(l2);
|
||||
tcg_temp_free(temp);
|
||||
if (unlikely(Rc(ctx->opcode) != 0))
|
||||
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*** Floating-Point arithmetic ***/
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue