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C99 64 bit printf

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2018 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2006-06-25 18:15:32 +00:00
parent 3b42c9794c
commit 26a76461f2
25 changed files with 67 additions and 64 deletions
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16
target-sparc/helper.c
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@ -394,7 +394,7 @@ static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical
env->dmmuregs[4] = address; /* Fault address register */
env->exception_index = TT_DFAULT;
#ifdef DEBUG_MMU
printf("DFAULT at 0x%llx\n", address);
printf("DFAULT at 0x%" PRIx64 "\n", address);
#endif
return 1;
}
@ -406,7 +406,7 @@ static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical
}
}
#ifdef DEBUG_MMU
printf("DMISS at 0x%llx\n", address);
printf("DMISS at 0x%" PRIx64 "\n", address);
#endif
env->exception_index = TT_DMISS;
return 1;
@ -452,7 +452,7 @@ static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical
env->immuregs[3] |= (is_user << 3) | 1;
env->exception_index = TT_TFAULT;
#ifdef DEBUG_MMU
printf("TFAULT at 0x%llx\n", address);
printf("TFAULT at 0x%" PRIx64 "\n", address);
#endif
return 1;
}
@ -462,7 +462,7 @@ static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical
}
}
#ifdef DEBUG_MMU
printf("TMISS at 0x%llx\n", address);
printf("TMISS at 0x%" PRIx64 "\n", address);
#endif
env->exception_index = TT_TMISS;
return 1;
@ -491,7 +491,7 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
virt_addr = address & TARGET_PAGE_MASK;
vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
#ifdef DEBUG_MMU
printf("Translate at 0x%llx -> 0x%llx, vaddr 0x%llx\n", address, paddr, vaddr);
printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
#endif
ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
return ret;
@ -506,7 +506,7 @@ void dump_mmu(CPUState *env)
unsigned int i;
const char *mask;
printf("MMU contexts: Primary: %lld, Secondary: %lld\n", env->dmmuregs[1], env->dmmuregs[2]);
printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]);
if ((env->lsu & DMMU_E) == 0) {
printf("DMMU disabled\n");
} else {
@ -528,7 +528,7 @@ void dump_mmu(CPUState *env)
break;
}
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %lld\n",
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
env->dtlb_tag[i] & ~0x1fffULL,
env->dtlb_tte[i] & 0x1ffffffe000ULL,
mask,
@ -560,7 +560,7 @@ void dump_mmu(CPUState *env)
break;
}
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %lld\n",
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
env->itlb_tag[i] & ~0x1fffULL,
env->itlb_tte[i] & 0x1ffffffe000ULL,
mask,