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target-mips: Add ASE DSP compare-pick instructions
Add MIPS ASE DSP Compare-Pick instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Jia Liu
Aurelien Jarno
parent
1cb6686cf9
commit
2669056024
3 changed files with 635 additions and 0 deletions
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@ -3167,6 +3167,239 @@ BIT_INSV(dinsv, 0x7F, 0x3F, target_long);
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#undef BIT_INSV
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/** DSP Compare-Pick Sub-class insns **/
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#define CMP_HAS_RET(name, func, split_num, filter, bit_size) \
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target_ulong helper_##name(target_ulong rs, target_ulong rt) \
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{ \
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uint32_t rs_t, rt_t; \
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uint8_t cc; \
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uint32_t temp = 0; \
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int i; \
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\
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for (i = 0; i < split_num; i++) { \
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rs_t = (rs >> (bit_size * i)) & filter; \
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rt_t = (rt >> (bit_size * i)) & filter; \
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cc = mipsdsp_##func(rs_t, rt_t); \
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temp |= cc << i; \
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} \
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\
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return (target_ulong)temp; \
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}
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CMP_HAS_RET(cmpgu_eq_qb, cmpu_eq, 4, MIPSDSP_Q0, 8);
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CMP_HAS_RET(cmpgu_lt_qb, cmpu_lt, 4, MIPSDSP_Q0, 8);
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CMP_HAS_RET(cmpgu_le_qb, cmpu_le, 4, MIPSDSP_Q0, 8);
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#ifdef TARGET_MIPS64
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CMP_HAS_RET(cmpgu_eq_ob, cmpu_eq, 8, MIPSDSP_Q0, 8);
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CMP_HAS_RET(cmpgu_lt_ob, cmpu_lt, 8, MIPSDSP_Q0, 8);
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CMP_HAS_RET(cmpgu_le_ob, cmpu_le, 8, MIPSDSP_Q0, 8);
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#endif
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#undef CMP_HAS_RET
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#define CMP_NO_RET(name, func, split_num, filter, bit_size) \
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void helper_##name(target_ulong rs, target_ulong rt, \
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CPUMIPSState *env) \
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{ \
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int##bit_size##_t rs_t, rt_t; \
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int##bit_size##_t flag = 0; \
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int##bit_size##_t cc; \
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int i; \
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\
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for (i = 0; i < split_num; i++) { \
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rs_t = (rs >> (bit_size * i)) & filter; \
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rt_t = (rt >> (bit_size * i)) & filter; \
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\
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cc = mipsdsp_##func((int32_t)rs_t, (int32_t)rt_t); \
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flag |= cc << i; \
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} \
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\
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set_DSPControl_24(flag, split_num, env); \
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}
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CMP_NO_RET(cmpu_eq_qb, cmpu_eq, 4, MIPSDSP_Q0, 8);
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CMP_NO_RET(cmpu_lt_qb, cmpu_lt, 4, MIPSDSP_Q0, 8);
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CMP_NO_RET(cmpu_le_qb, cmpu_le, 4, MIPSDSP_Q0, 8);
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CMP_NO_RET(cmp_eq_ph, cmp_eq, 2, MIPSDSP_LO, 16);
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CMP_NO_RET(cmp_lt_ph, cmp_lt, 2, MIPSDSP_LO, 16);
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CMP_NO_RET(cmp_le_ph, cmp_le, 2, MIPSDSP_LO, 16);
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#ifdef TARGET_MIPS64
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CMP_NO_RET(cmpu_eq_ob, cmpu_eq, 8, MIPSDSP_Q0, 8);
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CMP_NO_RET(cmpu_lt_ob, cmpu_lt, 8, MIPSDSP_Q0, 8);
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CMP_NO_RET(cmpu_le_ob, cmpu_le, 8, MIPSDSP_Q0, 8);
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CMP_NO_RET(cmp_eq_qh, cmp_eq, 4, MIPSDSP_LO, 16);
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CMP_NO_RET(cmp_lt_qh, cmp_lt, 4, MIPSDSP_LO, 16);
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CMP_NO_RET(cmp_le_qh, cmp_le, 4, MIPSDSP_LO, 16);
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CMP_NO_RET(cmp_eq_pw, cmp_eq, 2, MIPSDSP_LLO, 32);
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CMP_NO_RET(cmp_lt_pw, cmp_lt, 2, MIPSDSP_LLO, 32);
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CMP_NO_RET(cmp_le_pw, cmp_le, 2, MIPSDSP_LLO, 32);
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#endif
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#undef CMP_NO_RET
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#if defined(TARGET_MIPS64)
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#define CMPGDU_OB(name) \
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target_ulong helper_cmpgdu_##name##_ob(target_ulong rs, target_ulong rt, \
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CPUMIPSState *env) \
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{ \
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int i; \
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uint8_t rs_t, rt_t; \
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uint32_t cond; \
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\
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cond = 0; \
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\
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for (i = 0; i < 8; i++) { \
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rs_t = (rs >> (8 * i)) & MIPSDSP_Q0; \
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rt_t = (rt >> (8 * i)) & MIPSDSP_Q0; \
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\
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if (mipsdsp_cmpu_##name(rs_t, rt_t)) { \
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cond |= 0x01 << i; \
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} \
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} \
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\
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set_DSPControl_24(cond, 8, env); \
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\
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return (uint64_t)cond; \
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}
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CMPGDU_OB(eq)
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CMPGDU_OB(lt)
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CMPGDU_OB(le)
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#undef CMPGDU_OB
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#endif
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#define PICK_INSN(name, split_num, filter, bit_size, ret32bit) \
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target_ulong helper_##name(target_ulong rs, target_ulong rt, \
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CPUMIPSState *env) \
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{ \
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uint32_t rs_t, rt_t; \
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uint32_t cc; \
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target_ulong dsp; \
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int i; \
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target_ulong result = 0; \
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\
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dsp = env->active_tc.DSPControl; \
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for (i = 0; i < split_num; i++) { \
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rs_t = (rs >> (bit_size * i)) & filter; \
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rt_t = (rt >> (bit_size * i)) & filter; \
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cc = (dsp >> (24 + i)) & 0x01; \
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cc = cc == 1 ? rs_t : rt_t; \
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\
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result |= (target_ulong)cc << (bit_size * i); \
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} \
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\
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if (ret32bit) { \
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result = (target_long)(int32_t)(result & MIPSDSP_LLO); \
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} \
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\
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return result; \
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}
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PICK_INSN(pick_qb, 4, MIPSDSP_Q0, 8, 1);
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PICK_INSN(pick_ph, 2, MIPSDSP_LO, 16, 1);
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#ifdef TARGET_MIPS64
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PICK_INSN(pick_ob, 8, MIPSDSP_Q0, 8, 0);
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PICK_INSN(pick_qh, 4, MIPSDSP_LO, 16, 0);
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PICK_INSN(pick_pw, 2, MIPSDSP_LLO, 32, 0);
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#endif
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#undef PICK_INSN
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#define APPEND_INSN(name, ret_32) \
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target_ulong helper_##name(target_ulong rt, target_ulong rs, uint32_t sa) \
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{ \
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target_ulong temp; \
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\
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if (ret_32) { \
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temp = ((rt & MIPSDSP_LLO) << sa) | \
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((rs & MIPSDSP_LLO) & ((0x01 << sa) - 1)); \
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temp = (target_long)(int32_t)(temp & MIPSDSP_LLO); \
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} else { \
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temp = (rt << sa) | (rs & ((0x01 << sa) - 1)); \
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} \
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\
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return temp; \
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}
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APPEND_INSN(append, 1);
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#ifdef TARGET_MIPS64
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APPEND_INSN(dappend, 0);
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#endif
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#undef APPEND_INSN
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#define PREPEND_INSN(name, or_val, ret_32) \
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target_ulong helper_##name(target_ulong rs, target_ulong rt, \
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uint32_t sa) \
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{ \
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sa |= or_val; \
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\
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if (1) { \
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return (target_long)(int32_t)(uint32_t) \
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(((rs & MIPSDSP_LLO) << (32 - sa)) | \
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((rt & MIPSDSP_LLO) >> sa)); \
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} else { \
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return (rs << (64 - sa)) | (rt >> sa); \
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} \
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}
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PREPEND_INSN(prepend, 0, 1);
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#ifdef TARGET_MIPS64
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PREPEND_INSN(prependw, 0, 0);
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PREPEND_INSN(prependd, 0x20, 0);
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#endif
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#undef PREPEND_INSN
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#define BALIGN_INSN(name, filter, ret32) \
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target_ulong helper_##name(target_ulong rs, target_ulong rt, uint32_t bp) \
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{ \
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bp = bp & 0x03; \
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\
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if ((bp & 1) == 0) { \
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return rt; \
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} else { \
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if (ret32) { \
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return (target_long)(int32_t)((rt << (8 * bp)) | \
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(rs >> (8 * (4 - bp)))); \
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} else { \
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return (rt << (8 * bp)) | (rs >> (8 * (8 - bp))); \
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} \
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} \
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}
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BALIGN_INSN(balign, 0x03, 1);
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#if defined(TARGET_MIPS64)
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BALIGN_INSN(dbalign, 0x07, 0);
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#endif
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#undef BALIGN_INSN
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target_ulong helper_packrl_ph(target_ulong rs, target_ulong rt)
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{
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uint32_t rsl, rth;
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rsl = rs & MIPSDSP_LO;
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rth = (rt & MIPSDSP_HI) >> 16;
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return (target_long)(int32_t)((rsl << 16) | rth);
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}
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#if defined(TARGET_MIPS64)
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target_ulong helper_packrl_pw(target_ulong rs, target_ulong rt)
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{
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uint32_t rs0, rt1;
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rs0 = rs & MIPSDSP_LLO;
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rt1 = (rt >> 32) & MIPSDSP_LLO;
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return ((uint64_t)rs0 << 32) | (uint64_t)rt1;
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}
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#endif
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#undef MIPSDSP_LHI
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#undef MIPSDSP_LLO
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#undef MIPSDSP_HI
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