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q35: Correct typo BRDIGE -> BRIDGE
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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3 changed files with 18 additions and 18 deletions
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@ -125,8 +125,8 @@ typedef struct Q35PCIHost {
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#define MCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1)
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#define MCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3)
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#define MCH_HOST_BRDIGE_SMRAM 0x9d
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#define MCH_HOST_BRDIGE_SMRAM_SIZE 1
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#define MCH_HOST_BRIDGE_SMRAM 0x9d
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#define MCH_HOST_BRIDGE_SMRAM_SIZE 1
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#define MCH_HOST_BRIDGE_SMRAM_DEFAULT ((uint8_t)0x2)
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#define MCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6))
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#define MCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5))
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@ -140,16 +140,16 @@ typedef struct Q35PCIHost {
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#define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000
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#define MCH_HOST_BRIDGE_ESMRAMC 0x9e
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#define MCH_HOST_BRDIGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 6))
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#define MCH_HOST_BRDIGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 5))
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#define MCH_HOST_BRDIGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 4))
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#define MCH_HOST_BRDIGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 3))
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#define MCH_HOST_BRDIGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 2))
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#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
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#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
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#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
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#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
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#define MCH_HOST_BRDIGE_ESMRAMC_T_EN ((uint8_t)1)
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#define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 6))
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#define MCH_HOST_BRIDGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 5))
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#define MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 4))
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#define MCH_HOST_BRIDGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 3))
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#define MCH_HOST_BRIDGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 2))
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#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
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#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
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#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
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#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
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#define MCH_HOST_BRIDGE_ESMRAMC_T_EN ((uint8_t)1)
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/* D1:F0 PCIE* port*/
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#define MCH_PCIE_DEV 1
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