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tcg: Always define all of the TCGOpcode enum members.

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By always defining these symbols, we can eliminate a lot of ifdefs.

To allow this to be checked reliably, the semantics of the
TCG_TARGET_HAS_* macros must be changed from def/undef to true/false.
This allows even more ifdefs to be removed, converting them into
C if statements.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Richard Henderson 2011-08-17 14:11:46 -07:00 • committed by Blue Swirl
parent 8399ad59e7
commit 25c4d9cc84
14 changed files with 832 additions and 1003 deletions
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31
tcg/mips/tcg-target.h
View file

@ -78,23 +78,24 @@ enum {
#define TCG_TARGET_CALL_ALIGN_ARGS 1
/* optional instructions */
#define TCG_TARGET_HAS_div_i32
#define TCG_TARGET_HAS_not_i32
#define TCG_TARGET_HAS_nor_i32
#undef TCG_TARGET_HAS_rot_i32
#define TCG_TARGET_HAS_ext8s_i32
#define TCG_TARGET_HAS_ext16s_i32
#undef TCG_TARGET_HAS_bswap32_i32
#undef TCG_TARGET_HAS_bswap16_i32
#undef TCG_TARGET_HAS_andc_i32
#undef TCG_TARGET_HAS_orc_i32
#undef TCG_TARGET_HAS_eqv_i32
#undef TCG_TARGET_HAS_nand_i32
#define TCG_TARGET_HAS_div_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_nor_i32 1
#define TCG_TARGET_HAS_rot_i32 0
#define TCG_TARGET_HAS_ext8s_i32 1
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_bswap32_i32 0
#define TCG_TARGET_HAS_bswap16_i32 0
#define TCG_TARGET_HAS_andc_i32 0
#define TCG_TARGET_HAS_orc_i32 0
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_deposit_i32 0
/* optional instructions automatically implemented */
#undef TCG_TARGET_HAS_neg_i32 /* sub rd, zero, rt */
#undef TCG_TARGET_HAS_ext8u_i32 /* andi rt, rs, 0xff */
#undef TCG_TARGET_HAS_ext16u_i32 /* andi rt, rs, 0xffff */
#define TCG_TARGET_HAS_neg_i32 0 /* sub rd, zero, rt */
#define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */
#define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */
/* Note: must be synced with dyngen-exec.h */
#define TCG_AREG0 TCG_REG_S0