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target/arm: Use TRANS_FEAT for FMMLA

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Being able to specify the feature predicate in TRANS_FEAT
makes it easier to split trans_FMMLA by element size,
which also happens to simplify the decode.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-79-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-05-27 11:18:31 -07:00 • committed by Peter Maydell
parent 41bf9b6799
commit 25aee7cc3b
2 changed files with 7 additions and 27 deletions
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7
target/arm/sve.decode
View file

@ -1598,10 +1598,9 @@ SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx
USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm
### SVE2 floating point matrix multiply accumulate ### SVE2 floating point matrix multiply accumulate
{ BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_e0 FMMLA_s 01100100 10 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
FMMLA 01100100 .. 1 ..... 111 001 ..... ..... @rda_rn_rm FMMLA_d 01100100 11 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
}
### SVE2 Memory Gather Load Group ### SVE2 Memory Gather Load Group

27
target/arm/translate-sve.c
View file

@ -7318,29 +7318,10 @@ DO_SVE2_ZPZZ_FP(FMINP, fminp)
* SVE Integer Multiply-Add (unpredicated) * SVE Integer Multiply-Add (unpredicated)
*/ */
static bool trans_FMMLA(DisasContext *s, arg_rrrr_esz *a) TRANS_FEAT(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_s,
{ a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR)
gen_helper_gvec_4_ptr *fn; TRANS_FEAT(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_d,
a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR)
switch (a->esz) {
case MO_32:
if (!dc_isar_feature(aa64_sve_f32mm, s)) {
return false;
}
fn = gen_helper_fmmla_s;
break;
case MO_64:
if (!dc_isar_feature(aa64_sve_f64mm, s)) {
return false;
}
fn = gen_helper_fmmla_d;
break;
default:
return false;
}
return gen_gvec_fpst_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR);
}
static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = { static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = {
NULL, gen_helper_sve2_sqdmlal_zzzw_h, NULL, gen_helper_sve2_sqdmlal_zzzw_h,