motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-09-01 22:42:13 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/arm: Split arm_pre_translate_insn

Browse source 
Create arm_check_ss_active and arm_check_kernelpage.

Reverse the order of the tests.  While it doesn't matter in practice,
because only user-only has a kernel page and user-only never sets
ss_active, ss_active has priority over execution exceptions and it
is best to keep them in the proper order.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2021-11-03 00:03:46 -04:00 • committed by Peter Maydell
parent 0bb72bca7c
commit 258a00e5a4
1 changed files with 7 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

10
target/arm/translate.c
View file

@ -9502,7 +9502,7 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
dc->insn_start = tcg_last_op(); dc->insn_start = tcg_last_op();
} }
static bool arm_pre_translate_insn(DisasContext *dc) static bool arm_check_kernelpage(DisasContext *dc)
{ {
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
/* Intercept jump to the magic kernel page. */ /* Intercept jump to the magic kernel page. */
@ -9514,7 +9514,11 @@ static bool arm_pre_translate_insn(DisasContext *dc)
return true; return true;
} }
#endif #endif
return false;
}
static bool arm_check_ss_active(DisasContext *dc)
{
if (dc->ss_active && !dc->pstate_ss) { if (dc->ss_active && !dc->pstate_ss) {
/* Singlestep state is Active-pending. /* Singlestep state is Active-pending.
* If we're in this state at the start of a TB then either * If we're in this state at the start of a TB then either
@ -9551,7 +9555,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
uint32_t pc = dc->base.pc_next; uint32_t pc = dc->base.pc_next;
unsigned int insn; unsigned int insn;
if (arm_pre_translate_insn(dc)) { if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
dc->base.pc_next = pc + 4; dc->base.pc_next = pc + 4;
return; return;
} }
@ -9622,7 +9626,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
uint32_t insn; uint32_t insn;
bool is_16bit; bool is_16bit;
if (arm_pre_translate_insn(dc)) { if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
dc->base.pc_next = pc + 2; dc->base.pc_next = pc + 2;
return; return;
} }