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Add endianness as io mem parameter

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As stated before, devices can be little, big or native endian. The
target endianness is not of their concern, so we need to push things
down a level.

This patch adds a parameter to cpu_register_io_memory that allows a
device to choose its endianness. For now, all devices simply choose
native endian, because that's the same behavior as before.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Alexander Graf 2010-12-08 12:05:37 +01:00 • committed by Blue Swirl
parent dd310534e3
commit 2507c12ab0
154 changed files with 446 additions and 262 deletions
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11
hw/ppc405_uc.c
View file

@ -383,7 +383,8 @@ static void ppc4xx_opba_init(target_phys_addr_t base)
#ifdef DEBUG_OPBA
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(opba_read, opba_write, opba);
io = cpu_register_io_memory(opba_read, opba_write, opba,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x002, io);
qemu_register_reset(ppc4xx_opba_reset, opba);
}
@ -809,7 +810,8 @@ static void ppc405_gpio_init(target_phys_addr_t base)
#ifdef DEBUG_GPIO
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio);
io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x038, io);
qemu_register_reset(&ppc405_gpio_reset, gpio);
}
@ -1218,7 +1220,8 @@ static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
#ifdef DEBUG_I2C
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(i2c_read, i2c_write, i2c);
io = cpu_register_io_memory(i2c_read, i2c_write, i2c,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x011, io);
qemu_register_reset(ppc4xx_i2c_reset, i2c);
}
@ -1501,7 +1504,7 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
#ifdef DEBUG_GPT
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(gpt_read, gpt_write, gpt);
io = cpu_register_io_memory(gpt_read, gpt_write, gpt, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x0d4, io);
qemu_register_reset(ppc4xx_gpt_reset, gpt);
}