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target/openrisc: Tidy ppc/npc implementation

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The NPC SPR is really only supposed to be used for FPGA debugging.
It contains the same contents as PC, unless one plays games.  Follow
the or1ksim implementation in flushing delayed branch state when it
is changed.

The PPC SPR need not be updated every instruction, merely when we
exit the TB or attempt to read its contents.

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2016-04-05 11:41:48 -07:00
parent a8000cb480
commit 24c328521b
6 changed files with 39 additions and 55 deletions
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13
target/openrisc/gdbstub.c
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@ -34,8 +34,8 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
case 32: /* PPC */
return gdb_get_reg32(mem_buf, env->ppc);
case 33: /* NPC */
return gdb_get_reg32(mem_buf, env->npc);
case 33: /* NPC (equals PC) */
return gdb_get_reg32(mem_buf, env->pc);
case 34: /* SR */
return gdb_get_reg32(mem_buf, cpu_get_sr(env));
@ -68,8 +68,13 @@ int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
env->ppc = tmp;
break;
case 33: /* NPC */
env->npc = tmp;
case 33: /* NPC (equals PC) */
/* If setting PC to something different,
also clear delayed branch status. */
if (env->pc != tmp) {
env->pc = tmp;
env->flags = 0;
}
break;
case 34: /* SR */