motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-04 16:23:55 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

ppc/pnv: Implement ADU access to LPC space

Browse source 
One of the functions of the ADU is indirect memory access engines that
send and receive data via ADU registers.

This implements the ADU LPC memory access functionality sufficiently
for IBM proprietary firmware to access the UART and print characters
to the serial port as it does on real hardware.

This requires a linkage between adu and lpc, which allows adu to
perform memory access in the lpc space.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2024-04-17 14:50:13 +10:00
parent 53f18b3ef2
commit 24bd283bcc
5 changed files with 117 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

7
include/hw/ppc/pnv_adu.h
View file

@ -10,6 +10,7 @@
#define PPC_PNV_ADU_H
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_lpc.h"
#include "hw/qdev-core.h"
#define TYPE_PNV_ADU "pnv-adu"
@ -19,6 +20,12 @@ OBJECT_DECLARE_TYPE(PnvADU, PnvADUClass, PNV_ADU)
struct PnvADU {
DeviceState xd;
/* LPCMC (LPC Master Controller) access engine */
PnvLpcController *lpc;
uint64_t lpc_base_reg;
uint64_t lpc_cmd_reg;
uint64_t lpc_data_reg;
MemoryRegion xscom_regs;
};

5
include/hw/ppc/pnv_lpc.h
View file

@ -109,6 +109,11 @@ struct PnvLpcClass {
DeviceRealize parent_realize;
};
bool pnv_lpc_opb_read(PnvLpcController *lpc, uint32_t addr,
uint8_t *data, int sz);
bool pnv_lpc_opb_write(PnvLpcController *lpc, uint32_t addr,
uint8_t *data, int sz);
ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp);
int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset,
uint64_t lpcm_addr, uint64_t lpcm_size);