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hw/intc/armv7m_nvic: Implement SCR

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We were previously making the system control register (SCR)
just RAZ/WI. Although we don't implement the functionality
this register controls, we should at least provide the state,
including the banked state for v8M.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180209165810.6668-7-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2018-02-15 18:29:37 +00:00
parent 43bbce7fbe
commit 24ac0fb129
3 changed files with 27 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

12
target/arm/machine.c
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@ -226,6 +226,16 @@ static const VMStateDescription vmstate_m_csselr = {
}
};
static const VMStateDescription vmstate_m_scr = {
.name = "cpu/m/scr",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(env.v7m.scr[M_REG_NS], ARMCPU),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_m = {
.name = "cpu/m",
.version_id = 4,
@ -248,6 +258,7 @@ static const VMStateDescription vmstate_m = {
.subsections = (const VMStateDescription*[]) {
&vmstate_m_faultmask_primask,
&vmstate_m_csselr,
&vmstate_m_scr,
NULL
}
};
@ -411,6 +422,7 @@ static const VMStateDescription vmstate_m_security = {
VMSTATE_UINT32(env.sau.rnr, ARMCPU),
VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate),
VMSTATE_UINT32(env.sau.ctrl, ARMCPU),
VMSTATE_UINT32(env.v7m.scr[M_REG_S], ARMCPU),
VMSTATE_END_OF_LIST()
}
};