motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-11 03:24:58 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate)

Browse source 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181011205206.3552-8-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-10-24 07:50:19 +01:00 • committed by Peter Maydell
parent 32f91fb71f
commit 246fa4aca9
1 changed files with 39 additions and 28 deletions
Download patch file Download diff file Expand all files Collapse all files

67
target/arm/translate.c
View file

@ -6641,7 +6641,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
return 1; return 1;
} }
} else { /* (insn & 0x00380080) == 0 */ } else { /* (insn & 0x00380080) == 0 */
int invert; int invert, reg_ofs, vec_size;
if (q && (rd & 1)) { if (q && (rd & 1)) {
return 1; return 1;
} }
@ -6681,8 +6682,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
break; break;
case 14: case 14:
imm |= (imm << 8) | (imm << 16) | (imm << 24); imm |= (imm << 8) | (imm << 16) | (imm << 24);
if (invert) if (invert) {
imm = ~imm; imm = ~imm;
}
break; break;
case 15: case 15:
if (invert) { if (invert) {
@ -6692,36 +6694,45 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
| ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
break; break;
} }
if (invert) if (invert) {
imm = ~imm; imm = ~imm;
}
for (pass = 0; pass < (q ? 4 : 2); pass++) { reg_ofs = neon_reg_offset(rd, 0);
if (op & 1 && op < 12) { vec_size = q ? 16 : 8;
tmp = neon_load_reg(rd, pass);
if (invert) { if (op & 1 && op < 12) {
/* The immediate value has already been inverted, so if (invert) {
BIC becomes AND. */ /* The immediate value has already been inverted,
tcg_gen_andi_i32(tmp, tmp, imm); * so BIC becomes AND.
} else { */
tcg_gen_ori_i32(tmp, tmp, imm); tcg_gen_gvec_andi(MO_32, reg_ofs, reg_ofs, imm,
} vec_size, vec_size);
} else { } else {
/* VMOV, VMVN. */ tcg_gen_gvec_ori(MO_32, reg_ofs, reg_ofs, imm,
tmp = tcg_temp_new_i32(); vec_size, vec_size);
if (op == 14 && invert) { }
int n; } else {
uint32_t val; /* VMOV, VMVN. */
val = 0; if (op == 14 && invert) {
for (n = 0; n < 4; n++) { TCGv_i64 t64 = tcg_temp_new_i64();
if (imm & (1 << (n + (pass & 1) * 4)))
val |= 0xff << (n * 8); for (pass = 0; pass <= q; ++pass) {
} uint64_t val = 0;
tcg_gen_movi_i32(tmp, val); int n;
} else {
tcg_gen_movi_i32(tmp, imm); for (n = 0; n < 8; n++) {
} if (imm & (1 << (n + pass * 8))) {
val |= 0xffull << (n * 8);
}
}
tcg_gen_movi_i64(t64, val);
neon_store_reg64(t64, rd + pass);
}
tcg_temp_free_i64(t64);
} else {
tcg_gen_gvec_dup32i(reg_ofs, vec_size, vec_size, imm);
} }
neon_store_reg(rd, pass, tmp);
} }
} }
} else { /* (insn & 0x00800010 == 0x00800000) */ } else { /* (insn & 0x00800010 == 0x00800000) */