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target/arm: [tcg,a64] Port to translate_insn
Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002510079.22386.10164419868911710218.stgit@frigg.lan> [rth: Adjust for translate_insn interface change.] Signed-off-by: Richard Henderson <rth@twiddle.net>
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1 changed files with 43 additions and 28 deletions
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@ -11254,6 +11254,9 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,
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dc->is_ldex = false;
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dc->is_ldex = false;
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dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el);
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dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el);
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dc->next_page_start =
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(dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
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init_tmp_a64_array(dc);
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init_tmp_a64_array(dc);
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return max_insns;
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return max_insns;
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@ -11291,12 +11294,43 @@ static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
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return true;
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return true;
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}
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}
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static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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CPUARMState *env = cpu->env_ptr;
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if (dc->ss_active && !dc->pstate_ss) {
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/* Singlestep state is Active-pending.
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* If we're in this state at the start of a TB then either
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* a) we just took an exception to an EL which is being debugged
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* and this is the first insn in the exception handler
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* b) debug exceptions were masked and we just unmasked them
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* without changing EL (eg by clearing PSTATE.D)
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* In either case we're going to take a swstep exception in the
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* "did not step an insn" case, and so the syndrome ISV and EX
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* bits should be zero.
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*/
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assert(dc->base.num_insns == 1);
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gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),
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default_exception_el(dc));
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dc->base.is_jmp = DISAS_NORETURN;
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} else {
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disas_a64_insn(env, dc);
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}
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if (dc->base.is_jmp == DISAS_NEXT) {
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if (dc->ss_active || dc->pc >= dc->next_page_start) {
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dc->base.is_jmp = DISAS_TOO_MANY;
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}
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}
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dc->base.pc_next = dc->pc;
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}
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void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
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void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
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TranslationBlock *tb)
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TranslationBlock *tb)
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{
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{
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CPUARMState *env = cs->env_ptr;
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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target_ulong next_page_start;
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int max_insns;
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int max_insns;
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dc->base.tb = tb;
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dc->base.tb = tb;
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@ -11306,7 +11340,6 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
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dc->base.num_insns = 0;
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dc->base.num_insns = 0;
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dc->base.singlestep_enabled = cs->singlestep_enabled;
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dc->base.singlestep_enabled = cs->singlestep_enabled;
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next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
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max_insns = dc->base.tb->cflags & CF_COUNT_MASK;
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max_insns = dc->base.tb->cflags & CF_COUNT_MASK;
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if (max_insns == 0) {
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if (max_insns == 0) {
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max_insns = CF_COUNT_MASK;
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max_insns = CF_COUNT_MASK;
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@ -11342,42 +11375,24 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
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gen_io_start();
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gen_io_start();
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}
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}
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if (dc->ss_active && !dc->pstate_ss) {
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aarch64_tr_translate_insn(&dc->base, cs);
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/* Singlestep state is Active-pending.
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* If we're in this state at the start of a TB then either
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* a) we just took an exception to an EL which is being debugged
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* and this is the first insn in the exception handler
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* b) debug exceptions were masked and we just unmasked them
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* without changing EL (eg by clearing PSTATE.D)
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* In either case we're going to take a swstep exception in the
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* "did not step an insn" case, and so the syndrome ISV and EX
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* bits should be zero.
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*/
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assert(dc->base.num_insns == 1);
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gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),
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default_exception_el(dc));
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dc->base.is_jmp = DISAS_NORETURN;
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break;
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}
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disas_a64_insn(env, dc);
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if (tcg_check_temp_count()) {
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if (tcg_check_temp_count()) {
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fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
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fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
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dc->pc);
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dc->pc);
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}
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}
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if (!dc->base.is_jmp && (tcg_op_buf_full() || cs->singlestep_enabled ||
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singlestep || dc->base.num_insns >= max_insns)) {
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dc->base.is_jmp = DISAS_TOO_MANY;
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}
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/* Translation stops when a conditional branch is encountered.
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/* Translation stops when a conditional branch is encountered.
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* Otherwise the subsequent code could get translated several times.
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* Otherwise the subsequent code could get translated several times.
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* Also stop translation when a page boundary is reached. This
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* Also stop translation when a page boundary is reached. This
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* ensures prefetch aborts occur at the right place.
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* ensures prefetch aborts occur at the right place.
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*/
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*/
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} while (!dc->base.is_jmp && !tcg_op_buf_full() &&
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} while (!dc->base.is_jmp);
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!cs->singlestep_enabled &&
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!singlestep &&
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!dc->ss_active &&
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dc->pc < next_page_start &&
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dc->base.num_insns < max_insns);
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if (dc->base.tb->cflags & CF_LAST_IO) {
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if (dc->base.tb->cflags & CF_LAST_IO) {
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gen_io_end();
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gen_io_end();
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