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target/hppa: add TLB trace events
To ease TLB debugging add a few trace events, which are disabled by default so that there's no performance impact. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-5-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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4 changed files with 40 additions and 2 deletions
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@ -22,6 +22,7 @@
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "qom/cpu.h"
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#include "trace.h"
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#ifdef CONFIG_USER_ONLY
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int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
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@ -43,9 +44,12 @@ static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr)
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for (i = 0; i < ARRAY_SIZE(env->tlb); ++i) {
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hppa_tlb_entry *ent = &env->tlb[i];
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if (ent->va_b <= addr && addr <= ent->va_e) {
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trace_hppa_tlb_find_entry(env, ent + i, ent->entry_valid,
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ent->va_b, ent->va_e, ent->pa);
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return ent;
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}
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}
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trace_hppa_tlb_find_entry_not_found(env, addr);
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return NULL;
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}
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@ -55,6 +59,8 @@ static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent)
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unsigned i, n = 1 << (2 * ent->page_size);
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uint64_t addr = ent->va_b;
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trace_hppa_tlb_flush_ent(env, ent, ent->va_b, ent->va_e, ent->pa);
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for (i = 0; i < n; ++i, addr += TARGET_PAGE_SIZE) {
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/* Do not flush MMU_PHYS_IDX. */
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tlb_flush_page_by_mmuidx(cs, addr, 0xf);
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@ -169,6 +175,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
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egress:
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*pphys = phys;
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*pprot = prot;
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trace_hppa_tlb_get_physical_address(env, ret, prot, addr, phys);
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return ret;
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}
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@ -198,6 +205,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
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MMUAccessType type, int mmu_idx, uintptr_t retaddr)
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{
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HPPACPU *cpu = HPPA_CPU(cs);
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CPUHPPAState *env = &cpu->env;
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int prot, excp, a_prot;
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hwaddr phys;
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@ -213,9 +221,10 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
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break;
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}
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excp = hppa_get_physical_address(&cpu->env, addr, mmu_idx,
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excp = hppa_get_physical_address(env, addr, mmu_idx,
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a_prot, &phys, &prot);
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if (unlikely(excp >= 0)) {
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trace_hppa_tlb_fill_excp(env, addr, size, type, mmu_idx);
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/* Failure. Raise the indicated exception. */
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cs->exception_index = excp;
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if (cpu->env.psw & PSW_Q) {
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@ -226,6 +235,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
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cpu_loop_exit_restore(cs, retaddr);
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}
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trace_hppa_tlb_fill_success(env, addr & TARGET_PAGE_MASK,
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phys & TARGET_PAGE_MASK, size, type, mmu_idx);
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/* Success! Store the translation into the QEMU TLB. */
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tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
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prot, mmu_idx, TARGET_PAGE_SIZE);
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@ -259,6 +270,7 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
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empty->va_b = addr & TARGET_PAGE_MASK;
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empty->va_e = empty->va_b + TARGET_PAGE_SIZE - 1;
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empty->pa = extract32(reg, 5, 20) << TARGET_PAGE_BITS;
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trace_hppa_tlb_itlba(env, empty, empty->va_b, empty->va_e, empty->pa);
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}
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/* Insert (Insn/Data) TLB Protection. Note this is PA 1.1 only. */
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@ -280,6 +292,8 @@ void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
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ent->d = extract32(reg, 28, 1);
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ent->t = extract32(reg, 29, 1);
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ent->entry_valid = 1;
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trace_hppa_tlb_itlbp(env, ent, ent->access_id, ent->u, ent->ar_pl2,
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ent->ar_pl1, ent->ar_type, ent->b, ent->d, ent->t);
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}
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/* Purge (Insn/Data) TLB. This is explicitly page-based, and is
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@ -299,6 +313,7 @@ void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr)
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{
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CPUState *src = CPU(hppa_env_get_cpu(env));
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CPUState *cpu;
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trace_hppa_tlb_ptlb(env);
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run_on_cpu_data data = RUN_ON_CPU_TARGET_PTR(addr);
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CPU_FOREACH(cpu) {
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@ -314,7 +329,7 @@ void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr)
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void HELPER(ptlbe)(CPUHPPAState *env)
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{
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CPUState *src = CPU(hppa_env_get_cpu(env));
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trace_hppa_tlb_ptlbe(env);
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memset(env->tlb, 0, sizeof(env->tlb));
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tlb_flush_by_mmuidx(src, 0xf);
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}
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@ -335,8 +350,10 @@ target_ureg HELPER(lpa)(CPUHPPAState *env, target_ulong addr)
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if (excp == EXCP_DTLB_MISS) {
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excp = EXCP_NA_DTLB_MISS;
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}
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trace_hppa_tlb_lpa_failed(env, addr);
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hppa_dynamic_excp(env, excp, GETPC());
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}
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trace_hppa_tlb_lpa_success(env, addr, phys);
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return phys;
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}
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