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tcg: Widen CPUTLBEntry comparators to 64-bits
This makes CPUTLBEntry agnostic to the address size of the guest. When 32-bit addresses are in effect, we can simply read the low 32 bits of the 64-bit field. Similarly when we need to update the field for setting TLB_NOTDIRTY. For TCG backends that could in theory be big-endian, but in practice are not (arm, loongarch, riscv), use QEMU_BUILD_BUG_ON to document and ensure this is not accidentally missed. For s390x, which is always big-endian, use HOST_BIG_ENDIAN anyway, to document the reason for the adjustment. For sparc64 and ppc64, always perform a 64-bit load, and rely on the following 32-bit comparison to ignore the high bits. Rearrange mips and ppc if ladders for clarity. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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11 changed files with 67 additions and 51 deletions
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@ -334,18 +334,25 @@ static inline target_ulong tlb_read_idx(const CPUTLBEntry *entry,
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{
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/* Do not rearrange the CPUTLBEntry structure members. */
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QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_read) !=
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MMU_DATA_LOAD * TARGET_LONG_SIZE);
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MMU_DATA_LOAD * sizeof(uint64_t));
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QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_write) !=
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MMU_DATA_STORE * TARGET_LONG_SIZE);
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MMU_DATA_STORE * sizeof(uint64_t));
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QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) !=
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MMU_INST_FETCH * TARGET_LONG_SIZE);
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MMU_INST_FETCH * sizeof(uint64_t));
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const target_ulong *ptr = &entry->addr_idx[access_type];
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#if TCG_OVERSIZED_GUEST
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return *ptr;
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#if TARGET_LONG_BITS == 32
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/* Use qatomic_read, in case of addr_write; only care about low bits. */
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const uint32_t *ptr = (uint32_t *)&entry->addr_idx[access_type];
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ptr += HOST_BIG_ENDIAN;
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return qatomic_read(ptr);
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#else
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const uint64_t *ptr = &entry->addr_idx[access_type];
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# if TCG_OVERSIZED_GUEST
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return *ptr;
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# else
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/* ofs might correspond to .addr_write, so use qatomic_read */
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return qatomic_read(ptr);
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# endif
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#endif
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}
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