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esp: add trivial implementation of the ESP_RFLAGS register

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The bottom 5 bits contain the number of bytes remaining in the FIFO which is
trivial to implement with Fifo8 (the remaining bits are unimplemented and left
as 0 for now).

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20210304221103.6369-41-mark.cave-ayland@ilande.co.uk>
This commit is contained in:
Mark Cave-Ayland 2021-03-04 22:11:01 +00:00
parent 023666da79
commit 238ec4d7d4
1 changed files with 4 additions and 0 deletions
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4
hw/scsi/esp.c
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@ -818,6 +818,10 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
val = s->rregs[saddr]; val = s->rregs[saddr];
} }
break; break;
case ESP_RFLAGS:
/* Bottom 5 bits indicate number of bytes in FIFO */
val = fifo8_num_used(&s->fifo);
break;
default: default:
val = s->rregs[saddr]; val = s->rregs[saddr];
break; break;