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hw/arm/armsse: Add unimplemented-device stub for cache control registers

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The SSE-200 gives each CPU a register bank to use to control its
L1 instruction cache. Put in an unimplemented-device stub for this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190121185118.18550-18-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2019-02-01 14:55:43 +00:00
parent e0b00f1b92
commit 2357bca532
2 changed files with 39 additions and 1 deletions
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include/hw/arm/armsse.h
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@ -150,6 +150,7 @@ typedef struct ARMSSE {
UnimplementedDeviceState mhu[2];
UnimplementedDeviceState ppu[NUM_PPUS];
UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
/*
* 'container' holds all devices seen by all CPUs.