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target/riscv: Use true diff for gen_pc_plus_diff

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Reduce reliance on absolute values by using true pc difference for
gen_pc_plus_diff() to prepare for PC-relative translation.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2023-05-26 15:21:22 +08:00 • committed by Alistair Francis
parent 022c7550d9
commit 227fb82f99
3 changed files with 9 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

13
target/riscv/translate.c
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@ -226,8 +226,10 @@ static void decode_save_opc(DisasContext *ctx)
}
static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
target_ulong dest)
target_long diff)
{
target_ulong dest = ctx->base.pc_next + diff;
if (get_xl(ctx) == MXL_RV32) {
dest = (int32_t)dest;
}
@ -236,7 +238,7 @@ static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
static void gen_update_pc(DisasContext *ctx, target_long diff)
{
gen_pc_plus_diff(cpu_pc, ctx, ctx->base.pc_next + diff);
gen_pc_plus_diff(cpu_pc, ctx, diff);
}
static void generate_exception(DisasContext *ctx, int excp)
@ -547,14 +549,11 @@ static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t)
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
target_ulong next_pc;
/* check misaligned: */
next_pc = ctx->base.pc_next + imm;
if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) {
if ((next_pc & 0x3) != 0) {
if ((imm & 0x3) != 0) {
TCGv target_pc = tcg_temp_new();
gen_pc_plus_diff(target_pc, ctx, next_pc);
gen_pc_plus_diff(target_pc, ctx, imm);
gen_exception_inst_addr_mis(ctx, target_pc);
return;
}