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hw/intc/arm_gicv3: Add IRQ handling CPU interface registers

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Add the CPU interface registers which deal with acknowledging
and dismissing interrupts.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
Tested-by: Shannon Zhao <shannon.zhao@linaro.org>
Message-id: 1465915112-29272-19-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2016-06-17 15:23:48 +01:00
parent b1a0eb777d
commit 227a865366
3 changed files with 449 additions and 0 deletions
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5
hw/intc/gicv3_internal.h
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@ -159,6 +159,11 @@
#define ICC_CTLR_EL3_A3V (1U << 15)
#define ICC_CTLR_EL3_NDS (1U << 17)
/* Special interrupt IDs */
#define INTID_SECURE 1020
#define INTID_NONSECURE 1021
#define INTID_SPURIOUS 1023
/* Functions internal to the emulated GICv3 */
/**