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Introduce the architectural part of the Renesas RX
architecture emulation, developed by Yoshinori Sato. CI jobs results:127886344
664579420
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664579420
# gpg: Signature made Fri 20 Mar 2020 10:27:32 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/target_renesas_rx-20200320: Add rx-softmmu target/rx: Dump bytes for each insn during disassembly target/rx: Collect all bytes during disassembly target/rx: Emit all disassembly in one prt() target/rx: Use prt_ldmi for XCHG_mr disassembly target/rx: Replace operand with prt_ldmi in disassembler target/rx: Disassemble rx_index_addr into a string target/rx: RX disassembler target/rx: CPU definitions target/rx: TCG helpers target/rx: TCG translation MAINTAINERS: Add entry for the Renesas RX architecture hw/registerfields.h: Add 8bit and 16bit register macros Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
226cd20706
23 changed files with 5897 additions and 2 deletions
11
configure
vendored
11
configure
vendored
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@ -4227,7 +4227,7 @@ fi
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fdt_required=no
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for target in $target_list; do
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case $target in
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aarch64*-softmmu|arm*-softmmu|ppc*-softmmu|microblaze*-softmmu|mips64el-softmmu|riscv*-softmmu)
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aarch64*-softmmu|arm*-softmmu|ppc*-softmmu|microblaze*-softmmu|mips64el-softmmu|riscv*-softmmu|rx-softmmu)
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fdt_required=yes
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;;
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esac
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@ -7912,6 +7912,12 @@ case "$target_name" in
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mttcg=yes
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gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml"
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;;
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rx)
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TARGET_ARCH=rx
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bflt="yes"
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target_compiler=$cross_cc_rx
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gdb_xml_files="rx-core.xml"
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;;
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sh4|sh4eb)
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TARGET_ARCH=sh4
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bflt="yes"
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@ -8093,6 +8099,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
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riscv*)
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disas_config "RISCV"
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;;
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rx)
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disas_config "RX"
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;;
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s390*)
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disas_config "S390"
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;;
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