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target/tricore: Swap src and dst reg for RCRR_INSERT

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Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-10-kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2023-08-28 13:26:49 +02:00
parent 23fa6f56b3
commit 222ff2d358
3 changed files with 18 additions and 4 deletions
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8
target/tricore/translate.c
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@ -8223,12 +8223,12 @@ static void decode_32Bit_opc(DisasContext *ctx)
temp2 = tcg_temp_new(); /* width*/
temp3 = tcg_temp_new(); /* pos */
CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r2);
tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
tcg_gen_andi_tl(temp2, cpu_gpr_d[r2 + 1], 0x1f);
tcg_gen_andi_tl(temp3, cpu_gpr_d[r2], 0x1f);
gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, temp2, temp3);
break;
/* RCRW Format */
case OPCM_32_RCRW_MASK_INSERT: