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https://github.com/Motorhead1991/qemu.git
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ppc patch queue for 2022-12-21:
This queue contains a MAINTAINERS update, the implementation of the Freescale eSDHC, the introduction of the DEXCR/HDEXCR instructions and other assorted fixes (most of them for the e500 board). -----BEGIN PGP SIGNATURE----- iIwEABYKADQWIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCY6M//RYcZGFuaWVsaGI0 MTNAZ21haWwuY29tAAoJEDzZypbeAzFkaNABAKfQ/zpg2ugr/SmC7Ee9tnFNxDrq JsNw+roXpUZvnkUZAQCMRm4BxfaXhXikRaSL2ZfGRtybKXki5o3Ez+rLxISiAg== =gRo7 -----END PGP SIGNATURE----- Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into staging ppc patch queue for 2022-12-21: This queue contains a MAINTAINERS update, the implementation of the Freescale eSDHC, the introduction of the DEXCR/HDEXCR instructions and other assorted fixes (most of them for the e500 board). # gpg: Signature made Wed 21 Dec 2022 17:18:53 GMT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: issuer "danielhb413@gmail.com" # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu: target/ppc: Check DEXCR on hash{st, chk} instructions target/ppc: Implement the DEXCR and HDEXCR hw/ppc/e500: Move comment to more appropriate place hw/ppc/e500: Resolve variable shadowing hw/ppc/e500: Prefer local variable over qdev_get_machine() hw/ppc/virtex_ml507: Prefer local over global variable target/ppc/mmu_common: Fix table layout of "info tlb" HMP command target/ppc/mmu_common: Log which effective address had no TLB entry found hw/ppc/spapr: Reduce "vof.h" inclusion hw/ppc/vof: Do not include the full "cpu.h" target/ppc/kvm: Add missing "cpu.h" and "exec/hwaddr.h" hw/ppc/e500: Add Freescale eSDHC to e500plat hw/sd/sdhci: Support big endian SD host controller interfaces MAINTAINERS: downgrade PPC KVM/TCG CPUs and pSeries to 'Odd Fixes' Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
222059a0fc
20 changed files with 220 additions and 34 deletions
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@ -128,10 +128,12 @@ config E500
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select PFLASH_CFI01
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select PLATFORM_BUS
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select PPCE500_PCI
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select SDHCI
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select SERIAL
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select MPC_I2C
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select FDT_PPC
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select DS1338
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select UNIMP
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config E500PLAT
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bool
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@ -48,6 +48,8 @@
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#include "hw/net/fsl_etsec/etsec.h"
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#include "hw/i2c/i2c.h"
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#include "hw/irq.h"
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#include "hw/sd/sdhci.h"
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#include "hw/misc/unimp.h"
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#define EPAPR_MAGIC (0x45504150)
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#define DTC_LOAD_PAD 0x1800000
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@ -66,11 +68,14 @@
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#define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
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#define MPC8544_PCI_REGS_OFFSET 0x8000ULL
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#define MPC8544_PCI_REGS_SIZE 0x1000ULL
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#define MPC85XX_ESDHC_REGS_OFFSET 0x2e000ULL
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#define MPC85XX_ESDHC_REGS_SIZE 0x1000ULL
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#define MPC8544_UTIL_OFFSET 0xe0000ULL
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#define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
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#define MPC8544_I2C_REGS_OFFSET 0x3000ULL
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#define MPC8XXX_GPIO_IRQ 47
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#define MPC8544_I2C_IRQ 43
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#define MPC85XX_ESDHC_IRQ 72
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#define RTC_REGS_OFFSET 0x68
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#define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000)
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@ -203,6 +208,22 @@ static void dt_i2c_create(void *fdt, const char *soc, const char *mpic,
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g_free(i2c);
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}
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static void dt_sdhc_create(void *fdt, const char *parent, const char *mpic)
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{
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hwaddr mmio = MPC85XX_ESDHC_REGS_OFFSET;
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hwaddr size = MPC85XX_ESDHC_REGS_SIZE;
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int irq = MPC85XX_ESDHC_IRQ;
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g_autofree char *name = NULL;
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name = g_strdup_printf("%s/sdhc@%" PRIx64, parent, mmio);
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qemu_fdt_add_subnode(fdt, name);
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qemu_fdt_setprop(fdt, name, "sdhci,auto-cmd12", NULL, 0);
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qemu_fdt_setprop_phandle(fdt, name, "interrupt-parent", mpic);
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qemu_fdt_setprop_cells(fdt, name, "bus-width", 4);
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qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x2);
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qemu_fdt_setprop_cells(fdt, name, "reg", mmio, size);
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qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc");
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}
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typedef struct PlatformDevtreeData {
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void *fdt;
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@ -553,6 +574,10 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
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dt_rtc_create(fdt, "i2c", "rtc");
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/* sdhc */
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if (pmc->has_esdhc) {
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dt_sdhc_create(fdt, soc, mpic);
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}
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gutil = g_strdup_printf("%s/global-utilities@%llx", soc,
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MPC8544_UTIL_OFFSET);
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@ -692,7 +717,6 @@ static int ppce500_prep_device_tree(PPCE500MachineState *machine,
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kernel_base, kernel_size, true);
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}
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/* Create -kernel TLB entries for BookE. */
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hwaddr booke206_page_size_to_tlb(uint64_t size)
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{
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return 63 - clz64(size / KiB);
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@ -723,6 +747,7 @@ static uint64_t mmubooke_initial_mapsize(CPUPPCState *env)
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return (1ULL << 10 << tsize);
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}
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/* Create -kernel TLB entries for BookE. */
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static void mmubooke_create_initial_mapping(CPUPPCState *env)
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{
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ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
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@ -883,7 +908,7 @@ void ppce500_init(MachineState *machine)
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bool kernel_as_payload;
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hwaddr bios_entry = 0;
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target_long payload_size;
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struct boot_info *boot_info;
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struct boot_info *boot_info = NULL;
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int dt_size;
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int i;
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unsigned int smp_cpus = machine->smp.cpus;
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@ -938,7 +963,6 @@ void ppce500_init(MachineState *machine)
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/* Register reset handler */
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if (!i) {
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/* Primary CPU */
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struct boot_info *boot_info;
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boot_info = g_new0(struct boot_info, 1);
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qemu_register_reset(ppce500_cpu_reset, cpu);
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env->load_info = boot_info;
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@ -959,8 +983,7 @@ void ppce500_init(MachineState *machine)
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memory_region_add_subregion(address_space_mem, 0, machine->ram);
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dev = qdev_new("e500-ccsr");
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object_property_add_child(qdev_get_machine(), "e500-ccsr",
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OBJECT(dev));
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object_property_add_child(OBJECT(machine), "e500-ccsr", OBJECT(dev));
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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ccsr = CCSR(dev);
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ccsr_addr_space = &ccsr->ccsr_space;
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@ -982,7 +1005,8 @@ void ppce500_init(MachineState *machine)
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0, qdev_get_gpio_in(mpicdev, 42), 399193,
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serial_hd(1), DEVICE_BIG_ENDIAN);
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}
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/* I2C */
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/* I2C */
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dev = qdev_new("mpc-i2c");
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s = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(s, &error_fatal);
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@ -992,6 +1016,26 @@ void ppce500_init(MachineState *machine)
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i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
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i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET);
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/* eSDHC */
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if (pmc->has_esdhc) {
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create_unimplemented_device("esdhc",
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pmc->ccsrbar_base + MPC85XX_ESDHC_REGS_OFFSET,
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MPC85XX_ESDHC_REGS_SIZE);
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/*
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* Compatible with:
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* - SD Host Controller Specification Version 2.0 Part A2
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* (See MPC8569E Reference Manual)
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*/
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dev = qdev_new(TYPE_SYSBUS_SDHCI);
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qdev_prop_set_uint8(dev, "sd-spec-version", 2);
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qdev_prop_set_uint8(dev, "endianness", DEVICE_BIG_ENDIAN);
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s = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(s, &error_fatal);
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sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC85XX_ESDHC_IRQ));
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memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OFFSET,
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sysbus_mmio_get_region(s, 0));
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}
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/* General Utility device */
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dev = qdev_new("mpc8544-guts");
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@ -1002,7 +1046,7 @@ void ppce500_init(MachineState *machine)
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/* PCI */
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dev = qdev_new("e500-pcihost");
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object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev));
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object_property_add_child(OBJECT(machine), "pci-host", OBJECT(dev));
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qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot);
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qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
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s = SYS_BUS_DEVICE(dev);
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@ -1217,7 +1261,6 @@ void ppce500_init(MachineState *machine)
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}
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assert(dt_size < DTB_MAX_SIZE);
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boot_info = env->load_info;
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boot_info->entry = bios_entry;
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boot_info->dt_base = dt_base;
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boot_info->dt_size = dt_size;
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@ -27,6 +27,7 @@ struct PPCE500MachineClass {
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int mpic_version;
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bool has_mpc8xxx_gpio;
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bool has_esdhc;
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hwaddr platform_bus_base;
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hwaddr platform_bus_size;
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int platform_bus_first_irq;
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@ -86,6 +86,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data)
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pmc->fixup_devtree = e500plat_fixup_devtree;
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pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_42;
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pmc->has_mpc8xxx_gpio = true;
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pmc->has_esdhc = true;
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pmc->platform_bus_base = 0xf00000000ULL;
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pmc->platform_bus_size = 128 * MiB;
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pmc->platform_bus_first_irq = 5;
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@ -62,6 +62,7 @@
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#include "hw/ppc/fdt.h"
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#include "hw/ppc/spapr.h"
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#include "hw/ppc/spapr_vio.h"
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#include "hw/ppc/vof.h"
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#include "hw/qdev-properties.h"
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#include "hw/pci-host/spapr.h"
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#include "hw/pci/msi.h"
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@ -157,7 +157,7 @@ static int xilinx_load_device_tree(MachineState *machine,
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int r;
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const char *dtb_filename;
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dtb_filename = current_machine->dtb;
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dtb_filename = machine->dtb;
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if (dtb_filename) {
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fdt = load_device_tree(dtb_filename, &fdt_size);
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if (!fdt) {
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@ -308,6 +308,7 @@ extern const VMStateDescription sdhci_vmstate;
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#define SDHC_CAPAB_REG_DEFAULT 0x057834b4
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#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
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DEFINE_PROP_UINT8("endianness", _state, endianness, DEVICE_LITTLE_ENDIAN), \
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DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \
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DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \
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DEFINE_PROP_UINT8("vendor", _state, vendor, SDHCI_VENDOR_NONE), \
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@ -1329,7 +1329,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
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value >> shift, value >> shift);
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}
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static const MemoryRegionOps sdhci_mmio_ops = {
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static const MemoryRegionOps sdhci_mmio_le_ops = {
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.read = sdhci_read,
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.write = sdhci_write,
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.valid = {
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@ -1340,6 +1340,21 @@ static const MemoryRegionOps sdhci_mmio_ops = {
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static const MemoryRegionOps sdhci_mmio_be_ops = {
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.read = sdhci_read,
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.write = sdhci_write,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4,
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.unaligned = false
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},
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
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{
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ERRP_GUARD();
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@ -1367,8 +1382,6 @@ void sdhci_initfn(SDHCIState *s)
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s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
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s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
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s->io_ops = &sdhci_mmio_ops;
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}
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void sdhci_uninitfn(SDHCIState *s)
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@ -1384,10 +1397,23 @@ void sdhci_common_realize(SDHCIState *s, Error **errp)
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{
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ERRP_GUARD();
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switch (s->endianness) {
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case DEVICE_LITTLE_ENDIAN:
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s->io_ops = &sdhci_mmio_le_ops;
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break;
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case DEVICE_BIG_ENDIAN:
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s->io_ops = &sdhci_mmio_be_ops;
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break;
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default:
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error_setg(errp, "Incorrect endianness");
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return;
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}
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sdhci_init_readonly_registers(s, errp);
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if (*errp) {
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return;
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}
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s->buf_maxsz = sdhci_get_fifolen(s);
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s->fifo_buffer = g_malloc0(s->buf_maxsz);
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