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target/sparc: Move MULX to decodetree

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Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-01 22:46:24 -07:00
parent 420a187d80
commit 22188d7da8
2 changed files with 6 additions and 5 deletions
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3
target/sparc/insns.decode
View file

@ -31,6 +31,7 @@ CALL 01 i:s30
&r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool &r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool
@r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc @r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc
@r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=0
{ {
[ [
@ -165,6 +166,8 @@ ORN 10 ..... 0.0110 ..... . ............. @r_r_ri_cc
XORN 10 ..... 0.0111 ..... . ............. @r_r_ri_cc XORN 10 ..... 0.0111 ..... . ............. @r_r_ri_cc
ADDC 10 ..... 0.1000 ..... . ............. @r_r_ri_cc ADDC 10 ..... 0.1000 ..... . ............. @r_r_ri_cc
MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0
Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
{ {
# For v7, the entire simm13 field is present, but masked to 7 bits. # For v7, the entire simm13 field is present, but masked to 7 bits.

8
target/sparc/translate.c
View file

@ -4073,6 +4073,7 @@ static bool do_arith(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op,
void (*func_cc)(TCGv, TCGv, TCGv)) void (*func_cc)(TCGv, TCGv, TCGv))
{ {
if (a->cc) { if (a->cc) {
assert(cc_op >= 0);
return do_arith_int(dc, a, cc_op, func_cc, NULL); return do_arith_int(dc, a, cc_op, func_cc, NULL);
} }
return do_arith_int(dc, a, cc_op, func, funci); return do_arith_int(dc, a, cc_op, func, funci);
@ -4096,6 +4097,8 @@ TRANS(ANDN, ALL, do_logic, a, tcg_gen_andc_tl, NULL)
TRANS(ORN, ALL, do_logic, a, tcg_gen_orc_tl, NULL) TRANS(ORN, ALL, do_logic, a, tcg_gen_orc_tl, NULL)
TRANS(XORN, ALL, do_logic, a, tcg_gen_eqv_tl, NULL) TRANS(XORN, ALL, do_logic, a, tcg_gen_eqv_tl, NULL)
TRANS(MULX, 64, do_arith, a, -1, tcg_gen_mul_tl, tcg_gen_muli_tl, NULL)
static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a) static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a)
{ {
/* OR with %g0 is the canonical alias for MOV. */ /* OR with %g0 is the canonical alias for MOV. */
@ -4561,11 +4564,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
cpu_src1 = get_src1(dc, insn); cpu_src1 = get_src1(dc, insn);
cpu_src2 = get_src2(dc, insn); cpu_src2 = get_src2(dc, insn);
switch (xop & ~0x10) { switch (xop & ~0x10) {
#ifdef TARGET_SPARC64
case 0x9: /* V9 mulx */
tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
break;
#endif
case 0xa: /* umul */ case 0xa: /* umul */
CHECK_IU_FEATURE(dc, MUL); CHECK_IU_FEATURE(dc, MUL);
gen_op_umul(cpu_dst, cpu_src1, cpu_src2); gen_op_umul(cpu_dst, cpu_src1, cpu_src2);