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target/ppc: Fix support for "STOP light" states on POWER9
STOP must act differently based on PSSCR:EC on POWER9. When set, it acts like the P7/P8 power management instructions and wake up at 0x100 based on the wakeup conditions in LPCR. When PSSCR:EC is clear however it will wakeup at the next instruction after STOP (if EE is clear) or take the corresponding interrupts (if EE is set). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190215161648.9600-4-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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5 changed files with 35 additions and 6 deletions
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@ -414,6 +414,10 @@ struct ppc_slb_t {
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#define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */
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#define LPCR_HDICE PPC_BIT(63)
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/* PSSCR bits */
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#define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */
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#define PSSCR_EC PPC_BIT(43) /* Exit Criterion */
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#define msr_sf ((env->msr >> MSR_SF) & 1)
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#define msr_isf ((env->msr >> MSR_ISF) & 1)
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#define msr_shv ((env->msr >> MSR_SHV) & 1)
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@ -1110,9 +1114,11 @@ struct CPUPPCState {
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* instructions and SPRs are diallowed if MSR:HV is 0
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*/
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bool has_hv_mode;
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/* On P7/P8, set when in PM state, we need to handle resume
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* in a special way (such as routing some resume causes to
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* 0x100), so flag this here.
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/*
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* On P7/P8/P9, set when in PM state, we need to handle resume in
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* a special way (such as routing some resume causes to 0x100), so
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* flag this here.
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*/
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bool in_pm_state;
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#endif
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