mirror of
https://github.com/Motorhead1991/qemu.git
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Qtest pull request
- RISCV CSR test - migration recover changed to OOB - removal of dead code in test-x86-cpuid-compat -----BEGIN PGP SIGNATURE----- iQJEBAABCAAuFiEEqhtIsKIjJqWkw2TPx5jcdBvsMZ0FAmeKbx4QHGZhcm9zYXNA c3VzZS5kZQAKCRDHmNx0G+wxnRD7D/9v4ovvGn/IwSXjjpOpkjhCSgV8TMi1F61P hqB5TTCY8yejvT7JauplMUHmcJsVCNx+HF36D+YjxBjqrhQE8vzPRXgcLxHL9RX4 Kwgdk24kFKADE3gsiys9gOpwRhmtY0/2CT5LvitfJRMxUNPtm0Mr7qM3Z0Taeusu lxZgIMTBeNakpY5vua8nlLQ4r+/Df6S3TFFAaQ4UYab/T5zHVcjKaySXDlT1QXpp M+Be21jPxuUYJnKCSxMCUtuY9wkSPcITzJW91V+JxL9STSpsKpnQe10JWDRbwLBt /am2Jg5f8iFEblCwr5aQRMwXB+e/Y7K4qKPOUalj+weGnCXh9DmWPXnV6qzdZNO8 sePKoFj1AMtqbVf3iOpDBRkH8dECiDh1jHmflW1grF0BuOwOw8dKYW+i2qz9ZDiW rKWKfRcZZ059aOCQWqpMC9TGQ8osMC/v6GGJwiPBDLapGjnAm5d1683w4Z1l8tAg vf9yti2mpzK15PB6doEj/IuZr8WKWFMklizmMMZpXgHIUpjtm3JFKXX/jGHcD3KU E8F4ns3zPMlq7ncIwc6GADRB3XzEuzzuXAaEO8HMN0fYHevfnFIon749udyBDI/n a1/CTzTmchItwzgpdvcoiKO6gkg6DO9n08QULCMPSVCtl5KAlz5yuwxWGI/rM6u7 ixPi8i24oA== =i4AD -----END PGP SIGNATURE----- Merge tag 'qtest-20250117-pull-request' of https://gitlab.com/farosas/qemu into staging Qtest pull request - RISCV CSR test - migration recover changed to OOB - removal of dead code in test-x86-cpuid-compat # -----BEGIN PGP SIGNATURE----- # # iQJEBAABCAAuFiEEqhtIsKIjJqWkw2TPx5jcdBvsMZ0FAmeKbx4QHGZhcm9zYXNA # c3VzZS5kZQAKCRDHmNx0G+wxnRD7D/9v4ovvGn/IwSXjjpOpkjhCSgV8TMi1F61P # hqB5TTCY8yejvT7JauplMUHmcJsVCNx+HF36D+YjxBjqrhQE8vzPRXgcLxHL9RX4 # Kwgdk24kFKADE3gsiys9gOpwRhmtY0/2CT5LvitfJRMxUNPtm0Mr7qM3Z0Taeusu # lxZgIMTBeNakpY5vua8nlLQ4r+/Df6S3TFFAaQ4UYab/T5zHVcjKaySXDlT1QXpp # M+Be21jPxuUYJnKCSxMCUtuY9wkSPcITzJW91V+JxL9STSpsKpnQe10JWDRbwLBt # /am2Jg5f8iFEblCwr5aQRMwXB+e/Y7K4qKPOUalj+weGnCXh9DmWPXnV6qzdZNO8 # sePKoFj1AMtqbVf3iOpDBRkH8dECiDh1jHmflW1grF0BuOwOw8dKYW+i2qz9ZDiW # rKWKfRcZZ059aOCQWqpMC9TGQ8osMC/v6GGJwiPBDLapGjnAm5d1683w4Z1l8tAg # vf9yti2mpzK15PB6doEj/IuZr8WKWFMklizmMMZpXgHIUpjtm3JFKXX/jGHcD3KU # E8F4ns3zPMlq7ncIwc6GADRB3XzEuzzuXAaEO8HMN0fYHevfnFIon749udyBDI/n # a1/CTzTmchItwzgpdvcoiKO6gkg6DO9n08QULCMPSVCtl5KAlz5yuwxWGI/rM6u7 # ixPi8i24oA== # =i4AD # -----END PGP SIGNATURE----- # gpg: Signature made Fri 17 Jan 2025 09:54:22 EST # gpg: using RSA key AA1B48B0A22326A5A4C364CFC798DC741BEC319D # gpg: issuer "farosas@suse.de" # gpg: Good signature from "Fabiano Rosas <farosas@suse.de>" [unknown] # gpg: aka "Fabiano Almeida Rosas <fabiano.rosas@suse.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: AA1B 48B0 A223 26A5 A4C3 64CF C798 DC74 1BEC 319D * tag 'qtest-20250117-pull-request' of https://gitlab.com/farosas/qemu: tests/qtest/test-x86-cpuid-compat: Remove tests related to pc-i440fx-2.3 tests/qtest/migration: Use out-of-band execution for migrate-recover tests/qtest: Introduce qtest_init_with_env_and_capabilities() tests/qtest: QTest example for RISC-V CSR register target/riscv: Add RISC-V CSR qtest support Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
20fac491cf
9 changed files with 210 additions and 24 deletions
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@ -22,6 +22,8 @@
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "system/reset.h"
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#include "system/qtest.h"
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#include "qemu/cutils.h"
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#include "hw/sysbus.h"
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#include "target/riscv/cpu.h"
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#include "hw/qdev-properties.h"
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@ -41,6 +43,55 @@ static void riscv_harts_cpu_reset(void *opaque)
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cpu_reset(CPU(cpu));
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}
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#ifndef CONFIG_USER_ONLY
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static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val)
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{
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RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(cpu_num));
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CPURISCVState *env = &cpu->env;
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int ret = RISCV_EXCP_NONE;
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if (strcmp(cmd, "get_csr") == 0) {
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ret = riscv_csrr(env, csrno, (target_ulong *)val);
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} else if (strcmp(cmd, "set_csr") == 0) {
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ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val,
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MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
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}
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g_assert(ret == RISCV_EXCP_NONE);
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}
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static bool csr_qtest_callback(CharBackend *chr, gchar **words)
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{
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if (strcmp(words[0], "csr") == 0) {
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uint64_t cpu;
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uint64_t val;
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int rc, csr;
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rc = qemu_strtou64(words[2], NULL, 0, &cpu);
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g_assert(rc == 0);
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rc = qemu_strtoi(words[3], NULL, 0, &csr);
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g_assert(rc == 0);
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rc = qemu_strtou64(words[4], NULL, 0, &val);
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g_assert(rc == 0);
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csr_call(words[1], cpu, csr, &val);
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qtest_send_prefix(chr);
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qtest_sendf(chr, "OK 0 "TARGET_FMT_lx"\n", (target_ulong)val);
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return true;
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}
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return false;
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}
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static void riscv_cpu_register_csr_qtest_callback(void)
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{
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static GOnce once;
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g_once(&once, (GThreadFunc)qtest_set_command_cb, csr_qtest_callback);
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}
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#endif
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static bool riscv_hart_realize(RISCVHartArrayState *s, int idx,
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char *cpu_type, Error **errp)
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{
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@ -58,6 +109,10 @@ static void riscv_harts_realize(DeviceState *dev, Error **errp)
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s->harts = g_new0(RISCVCPU, s->num_harts);
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#ifndef CONFIG_USER_ONLY
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riscv_cpu_register_csr_qtest_callback();
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#endif
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for (n = 0; n < s->num_harts; n++) {
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if (!riscv_hart_realize(s, n, s->cpu_type, errp)) {
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return;
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@ -543,7 +543,9 @@ QTestState *qtest_init_without_qmp_handshake(const char *extra_args)
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return qtest_init_internal(qtest_qemu_binary(NULL), extra_args);
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}
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QTestState *qtest_init_with_env(const char *var, const char *extra_args)
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QTestState *qtest_init_with_env_and_capabilities(const char *var,
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const char *extra_args,
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QList *capabilities)
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{
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QTestState *s = qtest_init_internal(qtest_qemu_binary(var), extra_args);
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QDict *greeting;
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@ -551,11 +553,23 @@ QTestState *qtest_init_with_env(const char *var, const char *extra_args)
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/* Read the QMP greeting and then do the handshake */
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greeting = qtest_qmp_receive(s);
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qobject_unref(greeting);
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qobject_unref(qtest_qmp(s, "{ 'execute': 'qmp_capabilities' }"));
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if (capabilities) {
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qtest_qmp_assert_success(s,
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"{ 'execute': 'qmp_capabilities', "
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"'arguments': { 'enable': %p } }",
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qobject_ref(capabilities));
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} else {
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qtest_qmp_assert_success(s, "{ 'execute': 'qmp_capabilities' }");
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}
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return s;
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}
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QTestState *qtest_init_with_env(const char *var, const char *extra_args)
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{
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return qtest_init_with_env_and_capabilities(var, extra_args, NULL);
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}
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QTestState *qtest_init(const char *extra_args)
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{
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return qtest_init_with_env(NULL, extra_args);
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@ -1218,6 +1232,33 @@ uint64_t qtest_rtas_call(QTestState *s, const char *name,
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return 0;
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}
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static void qtest_rsp_csr(QTestState *s, uint64_t *val)
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{
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gchar **args;
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uint64_t ret;
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int rc;
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args = qtest_rsp_args(s, 3);
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rc = qemu_strtou64(args[1], NULL, 16, &ret);
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g_assert(rc == 0);
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rc = qemu_strtou64(args[2], NULL, 16, val);
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g_assert(rc == 0);
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g_strfreev(args);
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}
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uint64_t qtest_csr_call(QTestState *s, const char *name,
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uint64_t cpu, int csr,
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uint64_t *val)
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{
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qtest_sendf(s, "csr %s 0x%"PRIx64" %d 0x%"PRIx64"\n",
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name, cpu, csr, *val);
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qtest_rsp_csr(s, val);
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return 0;
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}
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void qtest_add_func(const char *str, void (*fn)(void))
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{
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gchar *path = g_strdup_printf("/%s/%s", qtest_get_arch(), str);
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@ -19,6 +19,7 @@
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#include "qapi/qmp/qobject.h"
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#include "qapi/qmp/qdict.h"
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#include "qapi/qmp/qlist.h"
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#include "libqmp.h"
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typedef struct QTestState QTestState;
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@ -68,6 +69,22 @@ QTestState *qtest_init(const char *extra_args);
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*/
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QTestState *qtest_init_with_env(const char *var, const char *extra_args);
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/**
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* qtest_init_with_env_and_capabilities:
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* @var: Environment variable from where to take the QEMU binary
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* @extra_args: Other arguments to pass to QEMU. CAUTION: these
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* arguments are subject to word splitting and shell evaluation.
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* @capabilities: list of QMP capabilities (strings) to enable
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*
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* Like qtest_init_with_env(), but enable specified capabilities during
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* hadshake.
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*
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* Returns: #QTestState instance.
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*/
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QTestState *qtest_init_with_env_and_capabilities(const char *var,
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const char *extra_args,
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QList *capabilities);
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/**
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* qtest_init_without_qmp_handshake:
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* @extra_args: other arguments to pass to QEMU. CAUTION: these
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@ -600,6 +617,20 @@ uint64_t qtest_rtas_call(QTestState *s, const char *name,
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uint32_t nargs, uint64_t args,
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uint32_t nret, uint64_t ret);
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/**
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* qtest_csr_call:
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* @s: #QTestState instance to operate on.
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* @name: name of the command to call.
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* @cpu: hart number.
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* @csr: CSR number.
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* @val: Value for reading/writing.
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*
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* Call an RISC-V CSR read/write function
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*/
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uint64_t qtest_csr_call(QTestState *s, const char *name,
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uint64_t cpu, int csr,
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uint64_t *val);
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/**
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* qtest_bufread:
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* @s: #QTestState instance to operate on.
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@ -274,7 +274,7 @@ qtests_s390x = \
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qtests_riscv32 = \
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(config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ? ['sifive-e-aon-watchdog-test'] : [])
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qtests_riscv64 = \
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qtests_riscv64 = ['riscv-csr-test'] + \
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(unpack_edk2_blobs ? ['bios-tables-test'] : [])
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qos_test_ss = ss.source_set()
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@ -194,6 +194,16 @@ static void cleanup(const char *filename)
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unlink(path);
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}
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static QList *migrate_start_get_qmp_capabilities(const MigrateStart *args)
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{
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QList *capabilities = qlist_new();
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if (args->oob) {
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qlist_append_str(capabilities, "oob");
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}
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return capabilities;
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}
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int migrate_start(QTestState **from, QTestState **to, const char *uri,
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MigrateStart *args)
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{
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@ -210,6 +220,7 @@ int migrate_start(QTestState **from, QTestState **to, const char *uri,
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const char *machine_alias, *machine_opts = "";
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g_autofree char *machine = NULL;
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const char *bootpath;
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g_autoptr(QList) capabilities = migrate_start_get_qmp_capabilities(args);
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if (args->use_shmem) {
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if (!g_file_test("/dev/shm", G_FILE_TEST_IS_DIR)) {
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@ -314,7 +325,8 @@ int migrate_start(QTestState **from, QTestState **to, const char *uri,
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args->opts_source ? args->opts_source : "",
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ignore_stderr);
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if (!args->only_target) {
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*from = qtest_init_with_env(QEMU_ENV_SRC, cmd_source);
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*from = qtest_init_with_env_and_capabilities(QEMU_ENV_SRC, cmd_source,
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capabilities);
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qtest_qmp_set_event_callback(*from,
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migrate_watch_for_events,
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&src_state);
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@ -334,7 +346,8 @@ int migrate_start(QTestState **from, QTestState **to, const char *uri,
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shmem_opts ? shmem_opts : "",
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args->opts_target ? args->opts_target : "",
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ignore_stderr);
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*to = qtest_init_with_env(QEMU_ENV_DST, cmd_target);
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*to = qtest_init_with_env_and_capabilities(QEMU_ENV_DST, cmd_target,
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capabilities);
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qtest_qmp_set_event_callback(*to,
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migrate_watch_for_events,
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&dst_state);
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@ -601,6 +614,12 @@ void test_postcopy_recovery_common(MigrateCommon *args)
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QTestState *from, *to;
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g_autofree char *uri = NULL;
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/*
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* Always enable OOB QMP capability for recovery tests, migrate-recover is
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* executed out-of-band
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*/
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args->start.oob = true;
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/* Always hide errors for postcopy recover tests since they're expected */
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args->start.hide_stderr = true;
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@ -109,6 +109,8 @@ typedef struct {
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const char *opts_target;
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/* suspend the src before migrating to dest. */
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bool suspend_me;
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/* enable OOB QMP capability */
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bool oob;
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} MigrateStart;
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typedef enum PostcopyRecoveryFailStage {
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@ -464,7 +464,7 @@ void migrate_continue(QTestState *who, const char *state)
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void migrate_recover(QTestState *who, const char *uri)
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{
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qtest_qmp_assert_success(who,
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"{ 'execute': 'migrate-recover', "
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"{ 'exec-oob': 'migrate-recover', "
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" 'id': 'recover-cmd', "
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" 'arguments': { 'uri': %s } }",
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uri);
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56
tests/qtest/riscv-csr-test.c
Normal file
56
tests/qtest/riscv-csr-test.c
Normal file
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@ -0,0 +1,56 @@
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/*
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* QTest testcase for RISC-V CSRs
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*
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* Copyright (c) 2024 Syntacore.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
|
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* Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "libqtest.h"
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#define CSR_MVENDORID 0xf11
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#define CSR_MISELECT 0x350
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static void run_test_csr(void)
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{
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uint64_t res;
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uint64_t val = 0;
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QTestState *qts = qtest_init("-machine virt -cpu veyron-v1");
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res = qtest_csr_call(qts, "get_csr", 0, CSR_MVENDORID, &val);
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g_assert_cmpint(res, ==, 0);
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g_assert_cmpint(val, ==, 0x61f);
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val = 0xff;
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res = qtest_csr_call(qts, "set_csr", 0, CSR_MISELECT, &val);
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g_assert_cmpint(res, ==, 0);
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val = 0;
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res = qtest_csr_call(qts, "get_csr", 0, CSR_MISELECT, &val);
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g_assert_cmpint(res, ==, 0);
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g_assert_cmpint(val, ==, 0xff);
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qtest_quit(qts);
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}
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||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
g_test_init(&argc, &argv, NULL);
|
||||
|
||||
qtest_add_func("/cpu/csr", run_test_csr);
|
||||
|
||||
return g_test_run();
|
||||
}
|
||||
|
|
@ -357,19 +357,6 @@ int main(int argc, char **argv)
|
|||
"486", "xstore=on", "pc-i440fx-2.7",
|
||||
"xlevel2", 0);
|
||||
}
|
||||
/*
|
||||
* QEMU 2.3.0 had auto-level enabled for CPUID[7], already,
|
||||
* and the compat code that sets default level shouldn't
|
||||
* disable the auto-level=7 code:
|
||||
*/
|
||||
if (qtest_has_machine("pc-i440fx-2.3")) {
|
||||
add_cpuid_test("x86/cpuid/auto-level7/pc-i440fx-2.3/off",
|
||||
"Penryn", NULL, "pc-i440fx-2.3",
|
||||
"level", 4);
|
||||
add_cpuid_test("x86/cpuid/auto-level7/pc-i440fx-2.3/on",
|
||||
"Penryn", "erms=on", "pc-i440fx-2.3",
|
||||
"level", 7);
|
||||
}
|
||||
if (qtest_has_machine("pc-i440fx-2.9")) {
|
||||
add_cpuid_test("x86/cpuid/auto-level7/pc-i440fx-2.9/off",
|
||||
"Conroe", NULL, "pc-i440fx-2.9",
|
||||
|
|
@ -384,11 +371,6 @@ int main(int argc, char **argv)
|
|||
* code on old machine-types. Just check that the compat code
|
||||
* is working correctly:
|
||||
*/
|
||||
if (qtest_has_machine("pc-i440fx-2.3")) {
|
||||
add_cpuid_test("x86/cpuid/xlevel-compat/pc-i440fx-2.3",
|
||||
"SandyBridge", NULL, "pc-i440fx-2.3",
|
||||
"xlevel", 0x8000000a);
|
||||
}
|
||||
if (qtest_has_machine("pc-i440fx-2.4")) {
|
||||
add_cpuid_test("x86/cpuid/xlevel-compat/pc-i440fx-2.4/npt-off",
|
||||
"SandyBridge", NULL, "pc-i440fx-2.4",
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue