motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-06 09:13:55 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target-mips: optimize gen_cl()

Browse source 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6932 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2009-03-29 01:18:16 +00:00
parent af4b6c54c1
commit 20e1fb525a
1 changed files with 11 additions and 15 deletions
Download patch file Download diff file Expand all files Collapse all files

26
target-mips/translate.c
View file

@ -2128,42 +2128,36 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
int rd, int rs) int rd, int rs)
{ {
const char *opn = "CLx"; const char *opn = "CLx";
TCGv t0 = tcg_temp_local_new(); TCGv t0;
if (rd == 0) { if (rd == 0) {
/* Treat as NOP. */ /* Treat as NOP. */
MIPS_DEBUG("NOP"); MIPS_DEBUG("NOP");
goto out; return;
} }
t0 = tcg_temp_new();
gen_load_gpr(t0, rs); gen_load_gpr(t0, rs);
switch (opc) { switch (opc) {
case OPC_CLO: case OPC_CLO:
gen_helper_clo(t0, t0); gen_helper_clo(cpu_gpr[rd], t0);
opn = "clo"; opn = "clo";
break; break;
case OPC_CLZ: case OPC_CLZ:
gen_helper_clz(t0, t0); gen_helper_clz(cpu_gpr[rd], t0);
opn = "clz"; opn = "clz";
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_DCLO: case OPC_DCLO:
gen_helper_dclo(t0, t0); gen_helper_dclo(cpu_gpr[rd], t0);
opn = "dclo"; opn = "dclo";
break; break;
case OPC_DCLZ: case OPC_DCLZ:
gen_helper_dclz(t0, t0); gen_helper_dclz(cpu_gpr[rd], t0);
opn = "dclz"; opn = "dclz";
break; break;
#endif #endif
default:
MIPS_INVAL(opn);
generate_exception(ctx, EXCP_RI);
goto out;
} }
gen_store_gpr(t0, rd);
MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]); MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
out:
tcg_temp_free(t0); tcg_temp_free(t0);
} }
@ -7711,7 +7705,8 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
case OPC_MUL: case OPC_MUL:
gen_arith(env, ctx, op1, rd, rs, rt); gen_arith(env, ctx, op1, rd, rs, rt);
break; break;
case OPC_CLZ ... OPC_CLO: case OPC_CLO:
case OPC_CLZ:
check_insn(env, ctx, ISA_MIPS32); check_insn(env, ctx, ISA_MIPS32);
gen_cl(ctx, op1, rd, rs); gen_cl(ctx, op1, rd, rs);
break; break;
@ -7728,7 +7723,8 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
/* Treat as NOP. */ /* Treat as NOP. */
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_DCLZ ... OPC_DCLO: case OPC_DCLO:
case OPC_DCLZ:
check_insn(env, ctx, ISA_MIPS64); check_insn(env, ctx, ISA_MIPS64);
check_mips_64(ctx); check_mips_64(ctx);
gen_cl(ctx, op1, rd, rs); gen_cl(ctx, op1, rd, rs);