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ppc/xive: introduce the XIVE interrupt thread context
Each POWER9 processor chip has a XIVE presenter that can generate four different exceptions to its threads: - hypervisor exception, - O/S exception - Event-Based Branch (EBB) - msgsnd (doorbell). Each exception has a state independent from the others called a Thread Interrupt Management context. This context is a set of registers which lets the thread handle priority management and interrupt acknowledgment among other things. The most important ones being : - Interrupt Priority Register (PIPR) - Interrupt Pending Buffer (IPB) - Current Processor Priority (CPPR) - Notification Source Register (NSR) These registers are accessible through a specific MMIO region, called the Thread Interrupt Management Area (TIMA), four aligned pages, each exposing a different view of the registers. First page (page address ending in 0b00) gives access to the entire context and is reserved for the ring 0 view for the physical thread context. The second (page address ending in 0b01) is for the hypervisor, ring 1 view. The third (page address ending in 0b10) is for the operating system, ring 2 view. The fourth (page address ending in 0b11) is for user level, ring 3 view. The thread interrupt context is modeled with a XiveTCTX object containing the values of the different exception registers. The TIMA region is mapped at the same address for each CPU. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater
David Gibson
parent
002686be42
commit
207d9fe985
3 changed files with 550 additions and 0 deletions
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@ -367,4 +367,48 @@ typedef struct XiveENDSource {
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void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
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void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon);
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/*
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* XIVE Thread interrupt Management (TM) context
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*/
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#define TYPE_XIVE_TCTX "xive-tctx"
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#define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX)
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/*
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* XIVE Thread interrupt Management register rings :
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*
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* QW-0 User event-based exception state
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* QW-1 O/S OS context for priority management, interrupt acks
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* QW-2 Pool hypervisor pool context for virtual processors dispatched
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* QW-3 Physical physical thread context and security context
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*/
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#define XIVE_TM_RING_COUNT 4
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#define XIVE_TM_RING_SIZE 0x10
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typedef struct XiveTCTX {
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DeviceState parent_obj;
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CPUState *cs;
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qemu_irq output;
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uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
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} XiveTCTX;
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/*
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* XIVE Thread Interrupt Management Aera (TIMA)
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*
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* This region gives access to the registers of the thread interrupt
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* management context. It is four page wide, each page providing a
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* different view of the registers. The page with the lower offset is
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* the most privileged and gives access to the entire context.
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*/
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#define XIVE_TM_HW_PAGE 0x0
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#define XIVE_TM_HV_PAGE 0x1
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#define XIVE_TM_OS_PAGE 0x2
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#define XIVE_TM_USER_PAGE 0x3
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extern const MemoryRegionOps xive_tm_ops;
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void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
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#endif /* PPC_XIVE_H */
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@ -23,6 +23,88 @@
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#define XIVE_SRCNO_INDEX(srcno) ((srcno) & 0x0fffffff)
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#define XIVE_SRCNO(blk, idx) ((uint32_t)(blk) << 28 | (idx))
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#define TM_SHIFT 16
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/* TM register offsets */
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#define TM_QW0_USER 0x000 /* All rings */
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#define TM_QW1_OS 0x010 /* Ring 0..2 */
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#define TM_QW2_HV_POOL 0x020 /* Ring 0..1 */
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#define TM_QW3_HV_PHYS 0x030 /* Ring 0..1 */
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/* Byte offsets inside a QW QW0 QW1 QW2 QW3 */
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#define TM_NSR 0x0 /* + + - + */
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#define TM_CPPR 0x1 /* - + - + */
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#define TM_IPB 0x2 /* - + + + */
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#define TM_LSMFB 0x3 /* - + + + */
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#define TM_ACK_CNT 0x4 /* - + - - */
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#define TM_INC 0x5 /* - + - + */
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#define TM_AGE 0x6 /* - + - + */
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#define TM_PIPR 0x7 /* - + - + */
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#define TM_WORD0 0x0
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#define TM_WORD1 0x4
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/*
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* QW word 2 contains the valid bit at the top and other fields
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* depending on the QW.
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*/
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#define TM_WORD2 0x8
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#define TM_QW0W2_VU PPC_BIT32(0)
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#define TM_QW0W2_LOGIC_SERV PPC_BITMASK32(1, 31) /* XX 2,31 ? */
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#define TM_QW1W2_VO PPC_BIT32(0)
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#define TM_QW1W2_OS_CAM PPC_BITMASK32(8, 31)
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#define TM_QW2W2_VP PPC_BIT32(0)
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#define TM_QW2W2_POOL_CAM PPC_BITMASK32(8, 31)
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#define TM_QW3W2_VT PPC_BIT32(0)
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#define TM_QW3W2_LP PPC_BIT32(6)
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#define TM_QW3W2_LE PPC_BIT32(7)
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#define TM_QW3W2_T PPC_BIT32(31)
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/*
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* In addition to normal loads to "peek" and writes (only when invalid)
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* using 4 and 8 bytes accesses, the above registers support these
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* "special" byte operations:
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*
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* - Byte load from QW0[NSR] - User level NSR (EBB)
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* - Byte store to QW0[NSR] - User level NSR (EBB)
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* - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access
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* - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0
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* otherwise VT||0000000
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* - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present)
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*
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* Then we have all these "special" CI ops at these offset that trigger
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* all sorts of side effects:
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*/
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#define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/
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#define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */
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#define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */
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#define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user
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* context */
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#define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */
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#define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS
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* context to reg */
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#define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool
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* context to reg*/
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#define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */
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#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd
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* line */
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#define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */
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#define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even
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* line */
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#define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */
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/* XXX more... */
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/* NSR fields for the various QW ack types */
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#define TM_QW0_NSR_EB PPC_BIT8(0)
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#define TM_QW1_NSR_EO PPC_BIT8(0)
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#define TM_QW3_NSR_HE PPC_BITMASK8(0, 1)
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#define TM_QW3_NSR_HE_NONE 0
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#define TM_QW3_NSR_HE_POOL 1
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#define TM_QW3_NSR_HE_PHYS 2
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#define TM_QW3_NSR_HE_LSI 3
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#define TM_QW3_NSR_I PPC_BIT8(2)
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#define TM_QW3_NSR_GRP_LVL PPC_BIT8(3, 7)
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/*
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* EAS (Event Assignment Structure)
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*
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