mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-09-09 00:07:57 -06:00
target/avr: Move cpu register accesses into system memory
Integrate the i/o 0x00-0x1f and 0x38-0x3f loopbacks into the cpu registers with normal address space accesses. We no longer need to trap accesses to the first page within avr_cpu_tlb_fill but can wait until a write occurs. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
a2860ff908
commit
204a7bd856
5 changed files with 138 additions and 153 deletions
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@ -23,6 +23,7 @@
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#include "qemu/qemu-print.h"
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#include "exec/exec-all.h"
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#include "exec/translation-block.h"
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#include "exec/address-spaces.h"
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#include "cpu.h"
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#include "disas/dis-asm.h"
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#include "tcg/debug-assert.h"
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@ -110,6 +111,8 @@ static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
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static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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CPUAVRState *env = cpu_env(cs);
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AVRCPU *cpu = env_archcpu(env);
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AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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@ -122,6 +125,19 @@ static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
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cpu_reset(cs);
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mcc->parent_realize(dev, errp);
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/*
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* Two blocks in the low data space loop back into cpu registers.
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*/
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memory_region_init_io(&cpu->cpu_reg1, OBJECT(cpu), &avr_cpu_reg1, env,
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"avr-cpu-reg1", 32);
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memory_region_add_subregion(get_system_memory(),
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OFFSET_DATA, &cpu->cpu_reg1);
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memory_region_init_io(&cpu->cpu_reg2, OBJECT(cpu), &avr_cpu_reg2, env,
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"avr-cpu-reg2", 8);
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memory_region_add_subregion(get_system_memory(),
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OFFSET_DATA + 0x58, &cpu->cpu_reg2);
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}
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static void avr_cpu_set_int(void *opaque, int irq, int level)
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@ -23,6 +23,7 @@
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#include "cpu-qom.h"
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#include "exec/cpu-defs.h"
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#include "exec/memory.h"
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#ifdef CONFIG_USER_ONLY
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#error "AVR 8-bit does not support user mode"
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@ -152,6 +153,9 @@ struct ArchCPU {
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CPUAVRState env;
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MemoryRegion cpu_reg1;
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MemoryRegion cpu_reg2;
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/* Initial value of stack pointer */
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uint32_t init_sp;
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};
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@ -252,6 +256,9 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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extern const MemoryRegionOps avr_cpu_reg1;
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extern const MemoryRegionOps avr_cpu_reg2;
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#include "exec/cpu-all.h"
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#endif /* QEMU_AVR_CPU_H */
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@ -108,7 +108,7 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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int prot, page_size = TARGET_PAGE_SIZE;
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int prot;
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uint32_t paddr;
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address &= TARGET_PAGE_MASK;
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@ -133,23 +133,9 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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/* Access to memory. */
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paddr = OFFSET_DATA + address;
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prot = PAGE_READ | PAGE_WRITE;
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if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
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/*
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* Access to CPU registers, exit and rebuilt this TB to use
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* full access in case it touches specially handled registers
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* like SREG or SP. For probing, set page_size = 1, in order
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* to force tlb_fill to be called for the next access.
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*/
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if (probe) {
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page_size = 1;
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} else {
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cpu_env(cs)->fullacc = 1;
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cpu_loop_exit_restore(cs, retaddr);
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}
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}
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}
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tlb_set_page(cs, address, paddr, prot, mmu_idx, page_size);
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tlb_set_page(cs, address, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
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return true;
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}
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@ -203,133 +189,77 @@ void helper_wdr(CPUAVRState *env)
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}
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/*
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* This function implements IN instruction
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*
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* It does the following
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* a. if an IO register belongs to CPU, its value is read and returned
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* b. otherwise io address is translated to mem address and physical memory
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* is read.
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* c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
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*
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* The first 32 bytes of the data space are mapped to the cpu regs.
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* We cannot write these from normal store operations because TCG
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* does not expect global temps to be modified -- a global may be
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* live in a host cpu register across the store. We can however
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* read these, as TCG does make sure the global temps are saved
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* in case the load operation traps.
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*/
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target_ulong helper_inb(CPUAVRState *env, uint32_t port)
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static uint64_t avr_cpu_reg1_read(void *opaque, hwaddr addr, unsigned size)
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{
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target_ulong data = 0;
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CPUAVRState *env = opaque;
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switch (port - 0x38) {
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case REG_38_RAMPD:
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data = 0xff & (env->rampD >> 16);
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break;
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case REG_38_RAMPX:
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data = 0xff & (env->rampX >> 16);
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break;
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case REG_38_RAMPY:
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data = 0xff & (env->rampY >> 16);
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break;
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case REG_38_RAMPZ:
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data = 0xff & (env->rampZ >> 16);
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break;
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case REG_38_EIDN:
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data = 0xff & (env->eind >> 16);
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break;
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case REG_38_SPL:
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data = env->sp & 0x00ff;
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break;
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case REG_38_SPH:
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data = env->sp >> 8;
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break;
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case REG_38_SREG:
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data = cpu_get_sreg(env);
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break;
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default:
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/* not a special register, pass to normal memory access */
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data = address_space_ldub(&address_space_memory,
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OFFSET_IO_REGISTERS + port,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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return data;
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assert(addr < 32);
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return env->r[addr];
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}
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/*
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* This function implements OUT instruction
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*
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* It does the following
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* a. if an IO register belongs to CPU, its value is written into the register
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* b. otherwise io address is translated to mem address and physical memory
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* is written.
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* c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
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*
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* The range 0x38-0x3f of the i/o space is mapped to cpu regs.
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* As above, we cannot write these from normal store operations.
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*/
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void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data)
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{
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data &= 0x000000ff;
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switch (port - 0x38) {
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static uint64_t avr_cpu_reg2_read(void *opaque, hwaddr addr, unsigned size)
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{
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CPUAVRState *env = opaque;
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switch (addr) {
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case REG_38_RAMPD:
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if (avr_feature(env, AVR_FEATURE_RAMPD)) {
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env->rampD = (data & 0xff) << 16;
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}
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break;
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return 0xff & (env->rampD >> 16);
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case REG_38_RAMPX:
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if (avr_feature(env, AVR_FEATURE_RAMPX)) {
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env->rampX = (data & 0xff) << 16;
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}
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break;
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return 0xff & (env->rampX >> 16);
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case REG_38_RAMPY:
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if (avr_feature(env, AVR_FEATURE_RAMPY)) {
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env->rampY = (data & 0xff) << 16;
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}
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break;
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return 0xff & (env->rampY >> 16);
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case REG_38_RAMPZ:
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if (avr_feature(env, AVR_FEATURE_RAMPZ)) {
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env->rampZ = (data & 0xff) << 16;
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}
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break;
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return 0xff & (env->rampZ >> 16);
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case REG_38_EIDN:
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env->eind = (data & 0xff) << 16;
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break;
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return 0xff & (env->eind >> 16);
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case REG_38_SPL:
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env->sp = (env->sp & 0xff00) | (data);
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break;
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return env->sp & 0x00ff;
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case REG_38_SPH:
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if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) {
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env->sp = (env->sp & 0x00ff) | (data << 8);
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}
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break;
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return 0xff & (env->sp >> 8);
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case REG_38_SREG:
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cpu_set_sreg(env, data);
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break;
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default:
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/* not a special register, pass to normal memory access */
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address_space_stb(&address_space_memory, OFFSET_IO_REGISTERS + port,
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data, MEMTXATTRS_UNSPECIFIED, NULL);
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return cpu_get_sreg(env);
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}
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g_assert_not_reached();
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}
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/*
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* this function implements LD instruction when there is a possibility to read
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* from a CPU register
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*/
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target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr)
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static void avr_cpu_trap_write(void *opaque, hwaddr addr,
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uint64_t data64, unsigned size)
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{
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uint8_t data;
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CPUAVRState *env = opaque;
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CPUState *cs = env_cpu(env);
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env->fullacc = false;
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env->fullacc = true;
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cpu_loop_exit_restore(cs, cs->mem_io_pc);
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}
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if (addr < NUMBER_OF_CPU_REGISTERS) {
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/* CPU registers */
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data = env->r[addr];
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} else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
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/* IO registers */
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data = helper_inb(env, addr - NUMBER_OF_CPU_REGISTERS);
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} else {
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/* memory */
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data = address_space_ldub(&address_space_memory, OFFSET_DATA + addr,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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return data;
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}
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const MemoryRegionOps avr_cpu_reg1 = {
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.read = avr_cpu_reg1_read,
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.write = avr_cpu_trap_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.min_access_size = 1,
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.valid.max_access_size = 1,
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};
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const MemoryRegionOps avr_cpu_reg2 = {
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.read = avr_cpu_reg2_read,
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.write = avr_cpu_trap_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.min_access_size = 1,
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.valid.max_access_size = 1,
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};
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/*
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* this function implements ST instruction when there is a possibility to write
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@ -339,19 +269,50 @@ void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr)
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{
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env->fullacc = false;
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/* Following logic assumes this: */
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assert(OFFSET_IO_REGISTERS == OFFSET_DATA +
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NUMBER_OF_CPU_REGISTERS);
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if (addr < NUMBER_OF_CPU_REGISTERS) {
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switch (addr) {
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case 0 ... 31:
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/* CPU registers */
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env->r[addr] = data;
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} else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
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/* IO registers */
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helper_outb(env, addr - NUMBER_OF_CPU_REGISTERS, data);
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} else {
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/* memory */
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break;
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case REG_38_RAMPD + 0x38 + NUMBER_OF_CPU_REGISTERS:
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if (avr_feature(env, AVR_FEATURE_RAMPD)) {
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env->rampD = data << 16;
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}
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break;
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case REG_38_RAMPX + 0x38 + NUMBER_OF_CPU_REGISTERS:
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if (avr_feature(env, AVR_FEATURE_RAMPX)) {
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env->rampX = data << 16;
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}
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break;
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case REG_38_RAMPY + 0x38 + NUMBER_OF_CPU_REGISTERS:
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if (avr_feature(env, AVR_FEATURE_RAMPY)) {
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env->rampY = data << 16;
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}
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break;
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case REG_38_RAMPZ + 0x38 + NUMBER_OF_CPU_REGISTERS:
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if (avr_feature(env, AVR_FEATURE_RAMPZ)) {
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env->rampZ = data << 16;
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}
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break;
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case REG_38_EIDN + 0x38 + NUMBER_OF_CPU_REGISTERS:
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env->eind = data << 16;
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break;
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case REG_38_SPL + 0x38 + NUMBER_OF_CPU_REGISTERS:
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env->sp = (env->sp & 0xff00) | data;
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break;
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case REG_38_SPH + 0x38 + NUMBER_OF_CPU_REGISTERS:
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if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) {
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env->sp = (env->sp & 0x00ff) | (data << 8);
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}
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break;
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case REG_38_SREG + 0x38 + NUMBER_OF_CPU_REGISTERS:
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cpu_set_sreg(env, data);
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break;
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default:
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address_space_stb(&address_space_memory, OFFSET_DATA + addr, data,
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MEMTXATTRS_UNSPECIFIED, NULL);
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break;
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}
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}
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@ -23,7 +23,4 @@ DEF_HELPER_1(debug, noreturn, env)
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DEF_HELPER_1(break, noreturn, env)
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DEF_HELPER_1(sleep, noreturn, env)
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DEF_HELPER_1(unsupported, noreturn, env)
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DEF_HELPER_3(outb, void, env, i32, i32)
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DEF_HELPER_2(inb, tl, env, i32)
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DEF_HELPER_3(fullwr, void, env, i32, i32)
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DEF_HELPER_2(fullrd, tl, env, i32)
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@ -194,6 +194,9 @@ static bool avr_have_feature(DisasContext *ctx, int feature)
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static bool decode_insn(DisasContext *ctx, uint16_t insn);
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#include "decode-insn.c.inc"
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static void gen_inb(DisasContext *ctx, TCGv data, int port);
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static void gen_outb(DisasContext *ctx, TCGv data, int port);
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/*
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* Arithmetic Instructions
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*/
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@ -1293,9 +1296,8 @@ static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a)
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static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a)
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{
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TCGv data = tcg_temp_new_i32();
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TCGv port = tcg_constant_i32(a->reg);
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gen_helper_inb(data, tcg_env, port);
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gen_inb(ctx, data, a->reg);
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tcg_gen_andi_tl(data, data, 1 << a->bit);
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ctx->skip_cond = TCG_COND_EQ;
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ctx->skip_var0 = data;
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@ -1311,9 +1313,8 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a)
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static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a)
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{
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TCGv data = tcg_temp_new_i32();
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TCGv port = tcg_constant_i32(a->reg);
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gen_helper_inb(data, tcg_env, port);
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gen_inb(ctx, data, a->reg);
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tcg_gen_andi_tl(data, data, 1 << a->bit);
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ctx->skip_cond = TCG_COND_NE;
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ctx->skip_var0 = data;
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@ -1502,11 +1503,18 @@ static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr)
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static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr)
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{
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if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) {
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gen_helper_fullrd(data, tcg_env, addr);
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} else {
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tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB);
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}
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static void gen_inb(DisasContext *ctx, TCGv data, int port)
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{
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gen_data_load(ctx, data, tcg_constant_i32(port + NUMBER_OF_CPU_REGISTERS));
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}
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static void gen_outb(DisasContext *ctx, TCGv data, int port)
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{
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gen_helper_fullwr(tcg_env, data,
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tcg_constant_i32(port + NUMBER_OF_CPU_REGISTERS));
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}
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/*
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@ -2126,9 +2134,8 @@ static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a)
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static bool trans_IN(DisasContext *ctx, arg_IN *a)
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{
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TCGv Rd = cpu_r[a->rd];
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TCGv port = tcg_constant_i32(a->imm);
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gen_helper_inb(Rd, tcg_env, port);
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gen_inb(ctx, Rd, a->imm);
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return true;
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}
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@ -2139,9 +2146,8 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a)
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static bool trans_OUT(DisasContext *ctx, arg_OUT *a)
|
||||
{
|
||||
TCGv Rd = cpu_r[a->rd];
|
||||
TCGv port = tcg_constant_i32(a->imm);
|
||||
|
||||
gen_helper_outb(tcg_env, port, Rd);
|
||||
gen_outb(ctx, Rd, a->imm);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -2407,11 +2413,10 @@ static bool trans_SWAP(DisasContext *ctx, arg_SWAP *a)
|
|||
static bool trans_SBI(DisasContext *ctx, arg_SBI *a)
|
||||
{
|
||||
TCGv data = tcg_temp_new_i32();
|
||||
TCGv port = tcg_constant_i32(a->reg);
|
||||
|
||||
gen_helper_inb(data, tcg_env, port);
|
||||
gen_inb(ctx, data, a->reg);
|
||||
tcg_gen_ori_tl(data, data, 1 << a->bit);
|
||||
gen_helper_outb(tcg_env, port, data);
|
||||
gen_outb(ctx, data, a->reg);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -2422,11 +2427,10 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a)
|
|||
static bool trans_CBI(DisasContext *ctx, arg_CBI *a)
|
||||
{
|
||||
TCGv data = tcg_temp_new_i32();
|
||||
TCGv port = tcg_constant_i32(a->reg);
|
||||
|
||||
gen_helper_inb(data, tcg_env, port);
|
||||
gen_inb(ctx, data, a->reg);
|
||||
tcg_gen_andi_tl(data, data, ~(1 << a->bit));
|
||||
gen_helper_outb(tcg_env, port, data);
|
||||
gen_outb(ctx, data, a->reg);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue