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ppc/pnv: turn PnvPHB3 into a PnvPHB backend
We need a handful of changes that needs to be done in a single swoop to turn PnvPHB3 into a PnvPHB backend. In the PnvPHB3, since the PnvPHB device implements PCIExpressHost and will hold the PCI bus, change PnvPHB3 parent to TYPE_DEVICE. There are a couple of instances in pnv_phb3.c that needs to access the PCI bus, so a phb_base pointer is added to allow access to the parent PnvPHB. The PnvPHB3 root port will now be connected to a PnvPHB object. In pnv.c, the powernv8 machine chip8 will now hold an array of PnvPHB objects. pnv_get_phb3_child() needs to be adapted to return the PnvPHB3 backend from the PnvPHB child. A global property is added in pnv_machine_power8_class_init() to ensure that all PnvPHBs are created with phb->version = 3. After all these changes we're still able to boot a powernv8 machine with default settings. The real gain will come with user created PnvPHB devices, coming up next. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20220624084921.399219-4-danielhb413@gmail.com>
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4 changed files with 26 additions and 30 deletions
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@ -11,6 +11,7 @@
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#include "qapi/visitor.h"
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#include "qapi/error.h"
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#include "hw/pci-host/pnv_phb3_regs.h"
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#include "hw/pci-host/pnv_phb.h"
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#include "hw/pci-host/pnv_phb3.h"
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#include "hw/pci/pcie_host.h"
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#include "hw/pci/pcie_port.h"
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@ -26,7 +27,7 @@
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static PCIDevice *pnv_phb3_find_cfg_dev(PnvPHB3 *phb)
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{
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PCIHostState *pci = PCI_HOST_BRIDGE(phb);
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PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
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uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3];
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uint8_t bus, devfn;
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@ -590,7 +591,7 @@ void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size)
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uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size)
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{
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PnvPHB3 *phb = opaque;
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PCIHostState *pci = PCI_HOST_BRIDGE(phb);
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PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
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uint64_t val;
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if ((off & 0xfffc) == PHB_CONFIG_DATA) {
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@ -1011,7 +1012,6 @@ void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb)
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static void pnv_phb3_realize(DeviceState *dev, Error **errp)
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{
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PnvPHB3 *phb = PNV_PHB3(dev);
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PCIHostState *pci = PCI_HOST_BRIDGE(dev);
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PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
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int i;
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@ -1056,11 +1056,6 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp)
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/* Controller Registers */
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memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb3_reg_ops, phb,
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"phb3-regs", 0x1000);
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pnv_phb3_bus_init(dev, phb);
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pnv_phb_attach_root_port(pci, TYPE_PNV_PHB3_ROOT_PORT,
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phb->phb_id, phb->chip_id);
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}
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void pnv_phb3_update_regions(PnvPHB3 *phb)
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@ -1085,38 +1080,26 @@ void pnv_phb3_update_regions(PnvPHB3 *phb)
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pnv_phb3_check_all_m64s(phb);
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}
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static const char *pnv_phb3_root_bus_path(PCIHostState *host_bridge,
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PCIBus *rootbus)
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{
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PnvPHB3 *phb = PNV_PHB3(host_bridge);
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snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x",
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phb->chip_id, phb->phb_id);
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return phb->bus_path;
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}
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static Property pnv_phb3_properties[] = {
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DEFINE_PROP_UINT32("index", PnvPHB3, phb_id, 0),
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DEFINE_PROP_UINT32("chip-id", PnvPHB3, chip_id, 0),
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DEFINE_PROP_LINK("chip", PnvPHB3, chip, TYPE_PNV_CHIP, PnvChip *),
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DEFINE_PROP_LINK("phb-base", PnvPHB3, phb_base, TYPE_PNV_PHB, PnvPHB *),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pnv_phb3_class_init(ObjectClass *klass, void *data)
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{
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PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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hc->root_bus_path = pnv_phb3_root_bus_path;
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dc->realize = pnv_phb3_realize;
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device_class_set_props(dc, pnv_phb3_properties);
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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dc->user_creatable = false;
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}
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static const TypeInfo pnv_phb3_type_info = {
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.name = TYPE_PNV_PHB3,
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.parent = TYPE_PCIE_HOST_BRIDGE,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(PnvPHB3),
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.class_init = pnv_phb3_class_init,
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.instance_init = pnv_phb3_instance_init,
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