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PPC64/TCG: Implement 'rfebb' instruction

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An Event-Based Branch (EBB) allows applications to change the NIA when a
event-based exception occurs. Event-based exceptions are enabled by
setting the Branch Event Status and Control Register (BESCR). If the
event-based exception is enabled when the exception occurs, an EBB
happens.

The following operations happens during an EBB:

- Global Enable (GE) bit of BESCR is set to 0;
- bits 0-61 of the Event-Based Branch Return Register (EBBRR) are set
to the the effective address of the NIA that would have executed if the EBB
didn't happen;
- Instruction fetch and execution will continue in the effective address
contained in the Event-Based Branch Handler Register (EBBHR).

The EBB Handler will process the event and then execute the Return From
Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then
redirects execution to the address pointed in EBBRR. This process is
described in the PowerISA v3.1, Book II, Chapter 6 [1].

This patch implements the rfebb instruction. Descriptions of all
relevant BESCR bits are also added - this patch is only using BESCR_GE,
but the next patches will use the remaining bits.

[1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-9-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Daniel Henrique Barboza 2021-12-17 17:57:19 +01:00 • committed by Cédric Le Goater
parent 7aeac354a6
commit 1f26c75191
6 changed files with 85 additions and 0 deletions
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13
target/ppc/cpu.h
View file

@ -392,6 +392,19 @@ typedef enum {
/* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */
#define CTRL_RUN PPC_BIT(63)
/* EBB/BESCR bits */
/* Global Enable */
#define BESCR_GE PPC_BIT(0)
/* External Event-based Exception Enable */
#define BESCR_EE PPC_BIT(30)
/* Performance Monitor Event-based Exception Enable */
#define BESCR_PME PPC_BIT(31)
/* External Event-based Exception Occurred */
#define BESCR_EEO PPC_BIT(62)
/* Performance Monitor Event-based Exception Occurred */
#define BESCR_PMEO PPC_BIT(63)
#define BESCR_INVALID PPC_BITMASK(32, 33)
/* LPCR bits */
#define LPCR_VPM0 PPC_BIT(0)
#define LPCR_VPM1 PPC_BIT(1)