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target/microblaze: Add the opcode-0x0-illegal CPU property

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Add the opcode-0x0-illegal CPU property to control if the core
should trap opcode zero as illegal.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Edgar E. Iglesias 2019-10-30 13:49:14 +01:00
parent 648db19685
commit 1ee1bd28fc
3 changed files with 7 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

6
target/microblaze/cpu.c
View file

@ -206,7 +206,9 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
(cpu->cfg.dopb_bus_exception ? (cpu->cfg.dopb_bus_exception ?
PVR2_DOPB_BUS_EXC_MASK : 0) | PVR2_DOPB_BUS_EXC_MASK : 0) |
(cpu->cfg.iopb_bus_exception ? (cpu->cfg.iopb_bus_exception ?
PVR2_IOPB_BUS_EXC_MASK : 0); PVR2_IOPB_BUS_EXC_MASK : 0) |
(cpu->cfg.opcode_0_illegal ?
PVR2_OPCODE_0x0_ILL_MASK : 0);
env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
PVR5_DCACHE_WRITEBACK_MASK : 0; PVR5_DCACHE_WRITEBACK_MASK : 0;
@ -274,6 +276,8 @@ static Property mb_properties[] = {
/* Enables bus exceptions on failed instruction fetches. */ /* Enables bus exceptions on failed instruction fetches. */
DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU, DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
cfg.iopb_bus_exception, false), cfg.iopb_bus_exception, false),
DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
cfg.opcode_0_illegal, false),
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL), DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),

1
target/microblaze/cpu.h
View file

@ -303,6 +303,7 @@ struct MicroBlazeCPU {
bool endi; bool endi;
bool dopb_bus_exception; bool dopb_bus_exception;
bool iopb_bus_exception; bool iopb_bus_exception;
bool opcode_0_illegal;
char *version; char *version;
uint8_t pvr; uint8_t pvr;
} cfg; } cfg;

2
target/microblaze/translate.c
View file

@ -1573,7 +1573,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
LOG_DIS("%8.8x\t", dc->ir); LOG_DIS("%8.8x\t", dc->ir);
if (ir == 0) { if (ir == 0) {
trap_illegal(dc, dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK); trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal);
/* Don't decode nop/zero instructions any further. */ /* Don't decode nop/zero instructions any further. */
return; return;
} }