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hw/misc/bcm2835_cprman: add a PLL skeleton implementation
There are 5 PLLs in the CPRMAN, namely PLL A, C, D, H and B. All of them take the xosc clock as input and produce a new clock. This commit adds a skeleton implementation for the PLLs as sub-devices of the CPRMAN. The PLLs are instantiated and connected internally to the main oscillator. Each PLL has 6 registers : CM, A2W_CTRL, A2W_ANA[0,1,2,3], A2W_FRAC. A write to any of them triggers a call to the (not yet implemented) pll_update function. If the main oscillator changes frequency, an update is also triggered. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Luc Michel
Peter Maydell
parent
fc14176ba2
commit
1e986e25d0
3 changed files with 281 additions and 0 deletions
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@ -21,6 +21,33 @@ DECLARE_INSTANCE_CHECKER(BCM2835CprmanState, CPRMAN,
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#define CPRMAN_NUM_REGS (0x2000 / sizeof(uint32_t))
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typedef enum CprmanPll {
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CPRMAN_PLLA = 0,
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CPRMAN_PLLC,
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CPRMAN_PLLD,
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CPRMAN_PLLH,
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CPRMAN_PLLB,
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CPRMAN_NUM_PLL
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} CprmanPll;
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typedef struct CprmanPllState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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CprmanPll id;
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uint32_t *reg_cm;
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uint32_t *reg_a2w_ctrl;
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uint32_t *reg_a2w_ana; /* ANA[0] .. ANA[3] */
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uint32_t prediv_mask; /* prediv bit in ana[1] */
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uint32_t *reg_a2w_frac;
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Clock *xosc_in;
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Clock *out;
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} CprmanPllState;
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struct BCM2835CprmanState {
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/*< private >*/
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SysBusDevice parent_obj;
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@ -28,6 +55,8 @@ struct BCM2835CprmanState {
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/*< public >*/
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MemoryRegion iomem;
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CprmanPllState plls[CPRMAN_NUM_PLL];
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uint32_t regs[CPRMAN_NUM_REGS];
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uint32_t xosc_freq;
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@ -12,8 +12,94 @@
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#include "hw/registerfields.h"
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#include "hw/misc/bcm2835_cprman.h"
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#define TYPE_CPRMAN_PLL "bcm2835-cprman-pll"
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DECLARE_INSTANCE_CHECKER(CprmanPllState, CPRMAN_PLL,
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TYPE_CPRMAN_PLL)
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/* Register map */
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/* PLLs */
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REG32(CM_PLLA, 0x104)
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FIELD(CM_PLLA, LOADDSI0, 0, 1)
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FIELD(CM_PLLA, HOLDDSI0, 1, 1)
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FIELD(CM_PLLA, LOADCCP2, 2, 1)
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FIELD(CM_PLLA, HOLDCCP2, 3, 1)
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FIELD(CM_PLLA, LOADCORE, 4, 1)
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FIELD(CM_PLLA, HOLDCORE, 5, 1)
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FIELD(CM_PLLA, LOADPER, 6, 1)
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FIELD(CM_PLLA, HOLDPER, 7, 1)
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FIELD(CM_PLLx, ANARST, 8, 1)
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REG32(CM_PLLC, 0x108)
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FIELD(CM_PLLC, LOADCORE0, 0, 1)
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FIELD(CM_PLLC, HOLDCORE0, 1, 1)
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FIELD(CM_PLLC, LOADCORE1, 2, 1)
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FIELD(CM_PLLC, HOLDCORE1, 3, 1)
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FIELD(CM_PLLC, LOADCORE2, 4, 1)
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FIELD(CM_PLLC, HOLDCORE2, 5, 1)
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FIELD(CM_PLLC, LOADPER, 6, 1)
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FIELD(CM_PLLC, HOLDPER, 7, 1)
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REG32(CM_PLLD, 0x10c)
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FIELD(CM_PLLD, LOADDSI0, 0, 1)
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FIELD(CM_PLLD, HOLDDSI0, 1, 1)
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FIELD(CM_PLLD, LOADDSI1, 2, 1)
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FIELD(CM_PLLD, HOLDDSI1, 3, 1)
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FIELD(CM_PLLD, LOADCORE, 4, 1)
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FIELD(CM_PLLD, HOLDCORE, 5, 1)
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FIELD(CM_PLLD, LOADPER, 6, 1)
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FIELD(CM_PLLD, HOLDPER, 7, 1)
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REG32(CM_PLLH, 0x110)
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FIELD(CM_PLLH, LOADPIX, 0, 1)
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FIELD(CM_PLLH, LOADAUX, 1, 1)
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FIELD(CM_PLLH, LOADRCAL, 2, 1)
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REG32(CM_PLLB, 0x170)
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FIELD(CM_PLLB, LOADARM, 0, 1)
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FIELD(CM_PLLB, HOLDARM, 1, 1)
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REG32(A2W_PLLA_CTRL, 0x1100)
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FIELD(A2W_PLLx_CTRL, NDIV, 0, 10)
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FIELD(A2W_PLLx_CTRL, PDIV, 12, 3)
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FIELD(A2W_PLLx_CTRL, PWRDN, 16, 1)
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FIELD(A2W_PLLx_CTRL, PRST_DISABLE, 17, 1)
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REG32(A2W_PLLC_CTRL, 0x1120)
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REG32(A2W_PLLD_CTRL, 0x1140)
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REG32(A2W_PLLH_CTRL, 0x1160)
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REG32(A2W_PLLB_CTRL, 0x11e0)
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REG32(A2W_PLLA_ANA0, 0x1010)
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REG32(A2W_PLLA_ANA1, 0x1014)
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FIELD(A2W_PLLx_ANA1, FB_PREDIV, 14, 1)
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REG32(A2W_PLLA_ANA2, 0x1018)
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REG32(A2W_PLLA_ANA3, 0x101c)
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REG32(A2W_PLLC_ANA0, 0x1030)
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REG32(A2W_PLLC_ANA1, 0x1034)
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REG32(A2W_PLLC_ANA2, 0x1038)
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REG32(A2W_PLLC_ANA3, 0x103c)
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REG32(A2W_PLLD_ANA0, 0x1050)
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REG32(A2W_PLLD_ANA1, 0x1054)
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REG32(A2W_PLLD_ANA2, 0x1058)
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REG32(A2W_PLLD_ANA3, 0x105c)
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REG32(A2W_PLLH_ANA0, 0x1070)
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REG32(A2W_PLLH_ANA1, 0x1074)
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FIELD(A2W_PLLH_ANA1, FB_PREDIV, 11, 1)
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REG32(A2W_PLLH_ANA2, 0x1078)
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REG32(A2W_PLLH_ANA3, 0x107c)
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REG32(A2W_PLLB_ANA0, 0x10f0)
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REG32(A2W_PLLB_ANA1, 0x10f4)
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REG32(A2W_PLLB_ANA2, 0x10f8)
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REG32(A2W_PLLB_ANA3, 0x10fc)
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REG32(A2W_PLLA_FRAC, 0x1200)
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FIELD(A2W_PLLx_FRAC, FRAC, 0, 20)
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REG32(A2W_PLLC_FRAC, 0x1220)
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REG32(A2W_PLLD_FRAC, 0x1240)
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REG32(A2W_PLLH_FRAC, 0x1260)
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REG32(A2W_PLLB_FRAC, 0x12e0)
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/*
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* This field is common to all registers. Each register write value must match
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* the CPRMAN_PASSWORD magic value in its 8 MSB.
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@ -21,4 +107,62 @@
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FIELD(CPRMAN, PASSWORD, 24, 8)
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#define CPRMAN_PASSWORD 0x5a
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/* PLL init info */
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typedef struct PLLInitInfo {
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const char *name;
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size_t cm_offset;
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size_t a2w_ctrl_offset;
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size_t a2w_ana_offset;
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uint32_t prediv_mask; /* Prediv bit in ana[1] */
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size_t a2w_frac_offset;
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} PLLInitInfo;
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#define FILL_PLL_INIT_INFO(pll_) \
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.cm_offset = R_CM_ ## pll_, \
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.a2w_ctrl_offset = R_A2W_ ## pll_ ## _CTRL, \
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.a2w_ana_offset = R_A2W_ ## pll_ ## _ANA0, \
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.a2w_frac_offset = R_A2W_ ## pll_ ## _FRAC
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static const PLLInitInfo PLL_INIT_INFO[] = {
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[CPRMAN_PLLA] = {
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.name = "plla",
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.prediv_mask = R_A2W_PLLx_ANA1_FB_PREDIV_MASK,
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FILL_PLL_INIT_INFO(PLLA),
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},
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[CPRMAN_PLLC] = {
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.name = "pllc",
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.prediv_mask = R_A2W_PLLx_ANA1_FB_PREDIV_MASK,
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FILL_PLL_INIT_INFO(PLLC),
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},
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[CPRMAN_PLLD] = {
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.name = "plld",
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.prediv_mask = R_A2W_PLLx_ANA1_FB_PREDIV_MASK,
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FILL_PLL_INIT_INFO(PLLD),
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},
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[CPRMAN_PLLH] = {
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.name = "pllh",
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.prediv_mask = R_A2W_PLLH_ANA1_FB_PREDIV_MASK,
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FILL_PLL_INIT_INFO(PLLH),
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},
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[CPRMAN_PLLB] = {
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.name = "pllb",
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.prediv_mask = R_A2W_PLLx_ANA1_FB_PREDIV_MASK,
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FILL_PLL_INIT_INFO(PLLB),
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},
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};
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#undef FILL_PLL_CHANNEL_INIT_INFO
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static inline void set_pll_init_info(BCM2835CprmanState *s,
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CprmanPllState *pll,
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CprmanPll id)
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{
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pll->id = id;
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pll->reg_cm = &s->regs[PLL_INIT_INFO[id].cm_offset];
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pll->reg_a2w_ctrl = &s->regs[PLL_INIT_INFO[id].a2w_ctrl_offset];
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pll->reg_a2w_ana = &s->regs[PLL_INIT_INFO[id].a2w_ana_offset];
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pll->prediv_mask = PLL_INIT_INFO[id].prediv_mask;
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pll->reg_a2w_frac = &s->regs[PLL_INIT_INFO[id].a2w_frac_offset];
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}
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#endif
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